Research And Design Of High Speed Folding And Interpolating Analog To Digital Converter

Analog-to-Digital Converter(ADC)is widely used in communication systems,radar,radio astronomy and Internet of Things systems,and is a key module of mixed signal processing systems.With the continuous development of communication systems,the continuous improvement of upstream and downstream speeds also requires the continuous improvement of the speed of high-speed analog-to-digital converters.Compared with other ADCs,Folding and Interpolating ADCs have the advantages of high speed and medium precision,and are widely used in various high-speed signal processing systems.Therefore,it is of far-reaching significance to study a high-speed,high-precision ADC.This thesis introduces the folding and interpolation techniques used in the folding and interpolation analog-to-digital converters,and summarizes the non-ideal factors that exist.Considering the scale of the circuit,various non-ideal factors and the design index of 8-bit precision,a system scheme of three-bit coarse quantization and five-bit fine quantization is designed.The traditional gate voltage bootstrap switch has been optimized and improved.CMOS switches are added to the bootstrap path to further increase the speed of the bootstrap path.As a front-end sampling circuit,the linearity of the sampling switch is improved,and it can be used at ultra-high speed.The accuracy is still guaranteed under the circumstances;the averaging technology is used to reduce the offset error of the preamplifier,and the simulation shows that the offset error is 2.5m V;the cascade folding technology is used to achieve high folding coefficient,and the folding circuit with high folding coefficient is divided into two Level realization,without affecting the speed of the circuit,reducing the matching requirements of the circuit,the use of multi-fold folding reduces the linearity requirements of the folding curve,avoiding the need to quantify the peaks and valleys of the folding curve,and at the same time,the entire system Transformed into a zero-crossing detection circuit,the requirements for the comparator are also reduced;the use of interpolation technology can effectively reduce the overall scale of the system,and ultimately reduce the scale of the folding circuit to 1/16.At the same time,an improved interpolation network is designed to increase The linear matching of the interpolation curve greatly reduces the interpolation error of the system;the coarse and fine coordinated coding is adopted,which effectively improves the conversion accuracy of the ADCThis design adopts TSMC 40 nm CMOS process,the power supply voltage is 1.1V,and the circuit and layout design of the folded interpolation analog-to-digital converter are completed.The simulation results after the circuit: when the input frequency is 68.36 MHz,the SFDR is 57.86 d B,and the SNDR is46.43 d B,ENOB is 7.42bit;when the input frequency is 1240.23 MHz,SFDR is 51.90 d B,SNDR is44.09 d B,ENOB is 7.03 bit.The power consumption is 218.4m W.