Research Of Data Calibration Technology Of High Speed Folding And Interpolating ADC Based On FPGA

In recent years,with the country's increasing emphasis on microelectronics and integrated circuit industry,the development of the entire integrated circuit industry has increased at an amazing speed.Among them,analog-to-digital converter(ADC),as a bridge connecting analog field and digital field,its development degree is deeply valued by people.With the increasing demand for ADCs,the requirements for ADC performance are also growing.However,due to the limitations of current design structure and process technology,the conversion results of ADC will have errors,so people began to develop calibration technology to improve the performance of ADC by means of compensation,close to the initial design goal.In this paper,an error calibration technology based on field programmable gate array(FPGA)is designed for a self-developed 5gsps 8bit folding and interpolation ADC.This paper first describes the research background and significance of this topic,as well as the research progress at home and abroad.Secondly,the principle of folding and interpolating ADC,the traditional folding and interpolation structure and the improved pipeline cascade structure are introduced.Four main errors of folding and interpolation ADC are analyzed:gain error,offset error,time sampling error and nonlinear error.Several calibration methods for the errors of folding and interpolation ADC are studied,and a new calibration technology for integral nonlinearity(INL)is proposed.Finally,the automatic calibration algorithm is realized on the combination platform of FPGA and ADC.The main work done by the author is as follows:(1)A new calibration algorithm for nonlinear error is proposed.The FPGA is used to automatically calculate the nonlinear errors based on the code density principle,and DAC registers are added to the folded circuit to compensate for the error.(2)The nonlinear error of ADC is extracted and calibrated manually to verify the feasibility of the calibration method.(3)The Verilog hardware language is used to implement the calibration algorithm in the FPGA,and the off-chip background automatic calibration function based on FPGA is completed.The INL automatic calibration algorithm proposed in this thesis has successfully raised the effective bit ENOB of 5gsps 8bit ADC from 6.8bits to 7.2bits,SFDR from 49dB to 60dB,and reduced the INL error of ADC from± 1LSB to ±0.5LSB.The static performance of ADC is improved successfully,which provides a practical basis for the realization of ADC with stronger performance and higher reliability.