Study And Design Of 10-bit High Speed ADC

High-speed ADC has a wide range of application requirements in electronic systems such as wireless communications,high-speed data acquisition,and radar.High-speed ADCs come in a variety of architectures.The folded-interpolation ADC inherits the highspeed features of the Flash ADC,reduces the number of comparators and preamplifiers,and reduces power consumption to a certain extent,making it suitable for ultra-high-speed applications.Pipeline-SAR ADC overcomes the problem of low speed of traditional SAR ADC,achieves high speed and low power consumption,and is a rapidly developing hybrid architecture high-speed ADC,which is a research hotspot in this field.In this thesis,the study and design of high-speed ADC is carried out.Firstly,a singlechannel 10-bit,800MS/s high-speed folded interpolation ADC is studied.(1)The key circuits,including the average resistance network,folder,comparator,etc.,are analyzed.(2)Design,and analyze the non-ideal and boundary effects of the folder in detail,and propose three solutions for the boundary effect.Secondly,the 10-bit 500MS/s PipelineSAR ADC is studied.(1)The selection of the system-level architecture of the PipelineSAR ADC is analyzed in detail.Based on the power consumption and linearity of the ADC,a two-stage structure is adopted for the ADC.The accuracy of each stage is selected.(2)The selection of CDAC unit capacitance in a two-stage SAR ADC is analyzed in detail from the aspects of sampling noise,capacitance matching and linearity.And consider the setup time of the DAC from the perspective of response speed.(3)This thesis adopts an optimized CDAC array switch,based on single-tube and transmission gates,transmitting three levels of VDD,GND,and Vcm,using fewer transistors to achieve faster transmission characteristics,increasing conversion speed while reducing power consumption.Based on the 0.18 um standard CMOS process,the high-speed folded-interpolation ADC of this thesis is simulated.Before the boundary effect is improved,the ENOB of the ADC is 6.93 bits and the SFDR is 46.92 dB.The ring-shaped average resistor network is applied and the redundant preamplifier is added.After designing a new type of boundary folder structure,the simulation results show that ENOB is 9.11,SFDR is increased to 61.66 dB,and the boundary effect is significantly improved.Based on the 65 nm CMOS process,the capacitor array switch is simulated,and the on-time of the switch to VDD and GND is 22.35 ps and 41.26 ps respectively.Based on the Matlab Simulink modeling and simulation platform,the Pipeline-SAR ADC is modeled and simulated.The overall circuit has an ENOB of 8.91 bits at the Nyquist input frequency and an ENOB of 9.02 bits at the input frequency of 100 MHz,which achieves better performance.