| Power dissipation is becoming an increasingly important issue in the design of analog-to-digital converter (ADC) as signal processing systems move into applications requiring either portability, or as in the case of some telecommunications, a high degree of parallelism. This research focuses on minimizing power dissipation in high-speed folding and interpolation analog-to-digital converters, which are needed in applications requiring both high data rates and low power dissipation, such as medical imaging, high-definition television, PDA and wireless communication devices.; Folding is an analog preprocessing technique to reduce the complexity and power dissipation of flash analog-to-digital conversion architectures. However, with the reduction of comparators in folding architectures, the power dissipation of the folding circuit itself becomes significant. A novel folding circuit called current steering folding amplifier was developed to further reduce the power dissipation of folding ADCs. A 100 Msamples/s 8-bit folding and interpolation ADC employing the current steering folding amplifier was designed and simulated in 5V 0.5 μm CMOS process. This folding ADC can achieve a low power dissipation of 45.5mW.; This dissertation concludes that the current steering folding amplifier can not only reduce the power dissipation of folding ADCs by minimizing the number of current sources but also enhance the resolution by eliminating the tail current matching requirement in the folding circuit. |
