8-bit 500MS/s High-Speed Folding And Interpolating Analog-to-Digital Converter

With the fast development of digital integrated circuits and high-speed signal process systems, high-speed analog-to-digital converters(ADC) are widely applied to test instrumentation, LCD driver, digital oscilloscope, digital communication and radar systems. As a bottleneck in the mixed-signal system design, high-speed ADC consumes a large chip erea, power budget and designing period. The capability of wide signal bandwidth processing and high-speed is the key of system development.Among a lot of ADC architectures, folding and interpolating technology possesses advantages of high-speed, low-power, small chip erea and easiness to be compatible with digital process, etc. Most of the folding and interpolating ADCs were realized in bipolar process before the mid 90's. With the development of the CMOS process and design technique, more and more folding and interpolating ADCs are realized in CMOS technology now.Based on the above researches, this dissertation focuses on the design of an 8-bit 500MS/s sampling rate folding and interpolating ADC. The main contributions can be concluded as follows:(1) The main issues in designing high-speed ADCs are discussed in detail, such as static and dynamic offset reduction, low supply-voltage operation, gain-bandwidth optimization, high-speed input signal feedthrough, and timing errors between different channels, etc. Design trade-offs among power, speed and chip area further tighten the stringent design requirement. It is also particular importance that such ADCs be implemented in standard CMOS process. All such design issues make the design of high-speed ADCs difficult.(2) The design considerations of folding and interpolating ADC's main building blocks are discussed in detail, such as folding preprocess, interpolation network, offset averaging technique, high-speed sample-and-hold circuit, comparator and digital error correction, etc.(3) The main building blocks of high-speed folding and interpolating ADC are designed, such as wide-bandwidth analog switch, fully-differential high-speed sample-and-hold circuit, hybrid high-speed comparator and bandgap circuit. A novel constant VGST low-distortion high-bandwidth analog switch is designed, its -3dB bandwidth can get to 11.67GHz, turn-on time is 2.98ns and turn-off time is 1.35ns. The high-speed sample-and-hold circuit use open architecture and use the input capacitance of preamplifiers as the hold capacitor which eliminates the effect of preamplifier's input capacitance on the performance of S/H circuit. A hybrid high-speed comparator is designed, the small-quiescent-current generator is added to fast the transition time from reset to compare and increase the speed of the comparator. A novel bandgap reference is designed, a negative-feedback clamp technology is proposed to fulfill clamp function instead of the differential amplifier in traditional counterparts, thus simplify the design, a regulated cascade configuration is used in the output to improve the power supply rejection ratio. All the key circuits can satisfy the performance requirements.(4) The designed ADC is implemented in SMIC 0.18μm 1P6M CMOS process. Simulation results show that there has no missing-code, and the maximum DNL is 0.47LSB, the maximum INL is 0.91LSB. At 500MHz sampling frequency and 241MHz input frequency, the SNDR is 40.79dB. The maximum effective number of bit(ENOB) is 7.43, while when the input frequency is 241MHz, ENOB becomes 6.48 bit.