Design And Research Of High Speed Folding And Interpolating Analog To Digital Converter

As the rapid development of the Wireless communication, computer technology and digital processing technology, the application of high-speed analog-to-digital converters (ADC) are becoming more and more widely. Nowdays, the data transmission and processing rate in Wireless communication system has been achieved GS/s or more, so the design of the ADC applicated in the system is also a huge challenge. For such a high rate of requirements, the folding and interpolating (F&I) ADC is a very good choice. The conversion rate of this ADC is similar to the full parallel ADC, and at the same time it is superior to the full parallel ADC in the respects of size and power consumption. So the study of F&I ADC has great significance in the field of high-speed ADC.In this thesis, the basic structure of F&I ADC is given, and the functions and circuit implementation methods are analyzed and researched respectively. And then the advantages and disadvantages of the different implementation methods is Compared. In full consideration the circuit scale and the complexity, through the theoretical analysis and calculation, the structure of the fine channel completes the low 5 bits and the coarse channel completes high 3 bits is identified. In order to optimize the speed and power consumption of traditional F&I ADC, the interstage pipelined structure and caseaded offset averaging technology fine and coarse channel joint encoding are all applicated in this F&I ADC. Three nand gate spark code correction method is put forward to encode key 6th bit, and the the reliability of the high speed digital coding in the process of transformation is improved. Then the design of key circuit modules of F&I ADC is introduced in detail, including Sampling and holding circuit, folding and interpolating circuit, reference voltage ladder and pre amplifier circuit, comparator circuit and digital encoding circuit.In this thesis, the final design of a IGS/s 8bit F&I ADC is completed in TSMC0.18μm CMOS technology. The design and simulation of each key circuit module is completed in Cadence IC platform. The whole circuit occupies 1.5×1.4mm2. The converter achieves SNDR of 45.09dB and SFDR of 53.17dB and ENOB of 7.20bit respectively at 1GS/s sampling rate, and the power consumption is 342mW. The test results show that the ADC can achieve the highest ENOB of 5.86 bit at 200 MS/s, and the ADC achieves 7.0 bit after digital calibration.