Design Of Folding And Interpolating ADC In High-Speed Communicating System

With the development of the wireless communication, the high-speed analog-to-digital converter (ADC) is very important. Considering the CMOS process and digital signal processing technology, high-speed and medium accuracy, among the different ADC topologies, the folding and interpolation ADC achieves more. With the folding and interpolation structure, the folding and interpolation ADC has several advantages, e.g. The areas and number of the comparators can be reduced. In this thesis, the folding and interpolation AD converter is studied, and a 8-bit-3.2 GSPS high-speed ADC is designed.Firstly, the basic ADC working principle and performance are introduced. Then considering the several design merits, such as precision, speed, area, and power consumption, the ADC system is finally identified, and the key modules of folding interpolating ADC are analyzed in details. After comparing the pros and cons of various ADC implementation methods, the ADC design issues are identified. This article uses the finite difference type bootstrap switch as sample and hold circuit. A new dummy tube is designed to improve the precision of it. Because of the application of low kick back noise comparator, the buffer is removed. It greatly reduces the power consumption of the system, so as the cascade and parallel folding structures. Interpolated resistance improves the linearity of the circuit. High self correction coding technique greatly reduces the complexity of coding circuit, and improves the accuracy of the conversion.Under the power supply voltage of 1.2 V, the function and performance of each module are simulated. At 200MHz input@3.2GSPS, the peak DNL, INL and the ENOB are 0.8LSB, 1.2LSB and 7.28 bit respectively. The dissipation power is about 80mW.