Research And Design On The Key Techniques Of Ultra-high Speed Folding & Interpolating ADC

In recent years, with the development of computer and microelectronics technology, ADC(Analog-to-Digital) technology has entered a period of rapid development. As a key component of analog signal and digital signal conversion, high speed (GSps) ADC is widely used in signal processing, radar,mobile communication and radio astronomy, etc. At the same time, high speed communication system and signal processing system put forward higher and higher requirements for the speed of digital converter.Therefore, the study of ultra high speed sigle-core ADC has imprtant value and significance.In this thesis, we introduced the basic principle of the ADC, mainly introduced the principle and system design ideas of the folding and interpolating ADCs. The main design content includes the ultra high-speed comparator circuit, other key modules of ultra high speed ADC and the digital correction circuit.In the ultra high-speed comparator circuit design, we designed a 40GSps comparator based on Hua Hong NEC 0.18?m SiGe BiCMOS. The simulation and test results show that the comparator works in 40GSps and the power consumption is 28mW. In other key circuit modules, the two level folding and interpolation structure is adopted, which can achieve the maximum degree of large folding and interpolation factor while maintaining a high bandwidth. In order to ensure the accuracy of the ADC, this design uses 5 bit DAC circuit and D flip-flop as the front digital correction circuit to improve the linearity of the circuit.Based on TSMC 0.18?m CMOS process, we completed the design of 1GSps 8bit ADC. The chip area is 1.4*1.5mm2, the post-simulation results show that the frequency of the input signal is Nyquist at 1GSps sampling rate, SNDR is 45.05dB. SFDR is 53dB, ENOB is 7.19 bit; the test results show that the ENOB is 6.48bit and the power consumption is 342mW when the frequency of input singnal is 100MHz and the sampling rate is 200MSps. Based on 90nm TSMC CMOS process, this thesis completed the design of folding and interpolating ADC system. The chip area is 0.93 * 0.93 mm2, the post simulation results show that the ENOB can reach 7.34bit when the sampling rate is 2GSps; when the sampling rate is 1GSps, the test results show that the ENOB is above 7 bit, the integral nonlinearity and differential nonlinearity is lower than 0.3LSB, SNDR is 45.93dB, SFDR is 50.84dB, the power consumption is 210mW.Due to the mismatch and nonlinear characteristics of the devices in the circuits, the outputs will be affected by some offsets and errors inevitably. In order to reduce the influence of offsets and errors to outputs, a digital background correction algorithm based on fitting data method to obtain the correction table is proposed in this thesis. The results show that this method is universal and can improve the ENOB of ADC effectively.At the end of this thesis, we study the principle and characteristics of the ultra-high speed ADCs. And on this basis, we designed a simulation system which can model various architectures of high speed ADC.This simulation system can analysis work flow of ADCs, the principle and nonlinear analysis of circuits.Meanwhile, it can show the influence of the circuits parameters on the system. Consequently, the simulation system has a great significance to research and design of the high speed ADC.