Research And Design Of A 12bit 1.6GSPS Folding And Interpolation ADC

With the continuous development of the information age,digital signal processing has become a hot research field.As an important link between the analog world and digital signals,the analog-to-digital converter?ADC?has attracted more and more attention,which has been widely used in wireless communication,radar,medical instruments,liquid crystal display and so on.With the rapid development of digital communication,how to design high-speed and high-precision ADC has become the key to the development of information industry.Folding and interpolating ADC has attracted extensive attention and research in recent years because of its relatively simple structure,high speed and high precision.In this thesis,a 12bit 1.6GSPS Folding and interpolating ADC has been designed.Firstly,this thesis introduces the research background,research content and research significance of the subject,and the development of ADC at home and abroad.Secondly,the principle and classification of analog-to-digital converters are summarized,and various structures are compared.Then,the principle of Folding and interpolating ADC is introduced,and the basic structure and non-ideal factors of each module is analyzed.Based on the 0.13?m BiCMOS process,a Folding and interpolating high-speed ADC with no digital calibration circuit has been designed.The circuit used a new four-stage cascade folding interpolation structure,which eliminates the influence of coarse channel.The main structure includes the sampling and holding circuit,the reference voltage circuit,the folding circuit,the interpolation circuit,the comparator circuit and the coding circuit.In the sample-and-hold circuit,an emitter following SEF switch was designed to realize high-speed and high-precision signal sampling with high linearity.Buffers is added at the front and back end to isolate the input and output of the signal and provide a large driving current for the back-end circuit.In the folding circuit design,average technology was used to increase redundancy amplifier and linearity of folding curve.In the interpolation circuit,the ring resistance network is used as the interpolation resistance,to restrain the boundary effect and reduce the offset of zero-crossing point.The simulation was based on the Cadence Spectre environment and 0.13?m BiCMOS process.With the sampling frequency of 1.6GSPS,the input frequency is793.87MHz and the amplitude is 0.5V_pp.And the results show that the Spur-Free Dynamic Range?SFDR?is 71.3dB,and the Sigal to Noise and Distortion Ratio?SNDR?is62.5dB and the Effective number of Bit?ENOB?is 10.16bit.All of the performance parameters achieved the expected goal.