Design Of 8-bit High-Speed Folding And Interpolating Analog-to-Digital Converter

With the wide use of high-speed analog-to-digital converters (ADC), research of high-speed ADCs becomes more and more important. Among various ADC structures, folding and interpolating ADC has the advantages of high-speed, low-power, small chip area and easiness to be compatible with digital process, etc. This dissertation focuses on the design of an 8-bit 200MS/s sampling rate folding and interpolating ADC.In the paper, the structure of the ADC is divided into two parts. One is a 4-bit fine quantization with two-stage cascade folding and interpolating structure. The other is a 4-bit coarse quantization with Flash structure. The design considerations of folding and interpolating ADC's main blocks are discussed in detail. And the circuits are also designed, such as folding preprocess, interpolation network, offset averaging technique, sample-and-hold circuit, comparator, differential reference voltage generator and digital error correction, and etc. All the key circuits can satisfy the performance requirements.The ADC designed in this paper is implemented in SMIC 0.18μm 1P6M CMOS process. Simulation results show that there is no missing-code. The maximum DNL is 0.51LSB, and the maximum INL is 0.83LSB. At 200MHz sampling frequency, the maximum effective number of bits (ENOB) is 7.31 bits, and the minimum effective number of bits is 6.58 bits.