Research And Design Of InP ADC With High-speed Sample-and-Hold Circuit Structure

With the development of information technology,the application of analog-to-digital converters(ADC)has become increasingly widespread.In products such as radars,ultra-wideband communication systems and high-performance digital oscilloscopes,the speed performance of the analog-to-digital converter is usually the bottleneck of the overall system performance,so the research on high-speed ADCs is highly valued.Currently,the processes used in high-speed ADCs can generally be divided into CMOS process and HBT process.Compared with the CMOS process,the HBT process has the advantages of faster electron mobility,better device matching performance,and higher transistor cut-off frequency.In particular,the In P HBT process is very suitable for the design of high-speed circuits.Therefore,this article will design an ADC based on the In P HBT process.In the choice of ADC architecture,after comparing several current mainstream high-speed ADC architectures,the folding-interpolating structure is finally chosen.The folding-interpolating ADC can be divided into three modules: sample-and-hold circuit,coarse quantization module and fine quantization module.For further,after the input signal passes through the sample-and-hold circuit,it is divided into two parallel signals to reach the coarse quantization module and the fine quantization module.This article will introduce the design of the sample-and-hold circuit and the coarse quantization module in detail.For further,the high-speed sample-and-hold circuit is an important module in the high-speed ADC and is the key to ensuring the performance of the entire ADC.After analyzing several high-speed sample-and-hold circuits and comparing their advantages and disadvantages,this article finally chooses an open-loop active sample-and-hold circuit as the final structure.This article introduces the non-ideal factors in the sample-and-hold circuit in detail and provides relevant countermeasures.In the specific circuit design,detailed theoretical derivation and circuit principle analysis are carried out.Regarding the design of the coarse quantization module,according to the requirements of the coarse and fine quantization collaborative coding,this article redesigns the entire coarse quantization module circuit,introduces the system-level design idea in detail,and gives the specific circuit design according to the idea,and finally performs it with simulation.It has been verified to prove that it meets the design requirements.This article finally designs an In P ADC with a folding-interpolating architecture with a resolution of 8 bits,of which the coarse quantization is 3 bits and the fine quantization is 5 bits.The sampling rate is 6GSps,the full swing of the input signal is1.6V,and the input signal bandwidth is 500 MHz.The post-simulation results show that when the input sine signal frequency is 539 MHz,the effective number of bits(ENOB)of the sample-and-hold circuit can reach 8.43 bit,the signal-to-noise and distortion ratio(SNDR)is 52.53 d B,and the spurious-free dynamic range(SFDR)is 54.90 d B,meeting the design requirements.For the coarse quantization module,the final design basically realizes the expected assumption,and the simulation results show that the function of coarse and fine quantization cooperative coding is basically realized.Finally,the overall ADC can achieve an effective number of 7.07 bits with a sampling rate of 6GSps and an input signal of 539 MHz,the total layout area is 5.82mm×5.27 mm,and the current consumption is 2.6A at a power supply voltage of 5V.