Researchand Design Of Clock Mesh In Ultradeep Submicron Technology

As the development of the integrated circuit (IC) process and the increasing ofsystem clock frequency, the effect of On Chip Variation (OCV) in the highperformance IC physical design becomes more remarkable. The more strictlyrequirement on clock skew has increased the difficulty of the clock tree synthesis(CTS). Under ultra-deep sub-micron technology, the conventional technique of CTScannot meet the clock skew requirement. However, the mesh structure of clocknetwork has smaller clock skew and is insensitive to OCV, which becomes verypopular in high performance sub-micron IC design.This thesis deeply researched the clock mesh synthesis including the structure ofclock mesh, theory and the design flow. A standard flow of preprocess, mesh networkconstruction and integral synthesis has been proposed. And the thesis hasrecommended a parameter selection method for the uncertain clock mesh density,mesh drivers’ size and number. This method is based on the estimation of a meshdensity that leads to minimum routing resources and the method of FO4(Fanout of4).Firstly, an initial value is determined to reduce the value range. Secondly, run fastsimulation of the clock mesh design based on different selection of parameters andgenerate the results of clock skew, insertion delay, clock mesh power consumptionand the routing resources. The best value could be selected after an overallcomparison.Based on this flow and method of parameter selection, the thesis proposed anexample of the clock mesh design and verification in the physical design of SMIC65nm Bit Coin IC, BES6501. BES6501concludes3million equivalent gates,128xsha256hash function arithmetic unit working on a system clock frequency500MHz.The hierarchical physical design has been applied in this chip with global clock treeand local clock mesh especially in sha256module. The results are compared with theconventional CTS. The clock skew is2.2%of the conventional CTS. The insertiondelay is35%of the CTS result. The timing closure result under OCV mode isbasically the same as BC_WC (Best Case_Worst Case) mode. This is because themesh network has balanced the clock skew and fewer stage of the premesh tree. Thecost is6%higher power consumption.This thesis has proved the feasibility of the methodology of clock mesh synthesisin IC physical design, which offers a good reference for clock mesh designin ultra-deep sub-micron technology.