Research And Application Of Clock Skew Compensation Technology

With the advancement of semiconductor process and technology, the frequency ofVLSI(very large scale integrated circuit) is becoming higher and higher, clock signaland its distribution network are given more attention. The timing performance ofsynchronous system circuit is mainly affected by data path delay and clock skew. Afterdata path delay has been optimized to a certain degree, clock skew turns out to be themain limiting factor.Although clock skew scheduling strategy is supported bycommercial EDA tools, however, it has been proved that there are still disadvantagesexisting when scheduling clock skew in EDA tools. Thus, it is an important topic thatshould be resolved immediately on how to use external methods to handle thedisadvantages of EDA tools.The topic is mostly based on currently used CTS(clock tree synthesis) method inEDI tools. Analysing the shortcoming of EDI tools, we proposed a clock skewcompensation technology which has a great practicability for given project, and makesobvious improvement in timing performance. The achievement of the technology is asfollows:1. According to the relationship between clock skew and timing performance, weimplemented a clock skew compensation technology based on EDI using clock skewstrategy. The essence of the technology is borrowing the timing margin from the criticalpath’s previous and next path to the critical path, thus optimizing timing of critical pathand improving the performance.2. The technology is edited by TCL language as a script, then embedded in thebasic physical backend design flow to realize the combination with EDI tool, thus omitsthe complex manpower work and improves the efficency of work. Set the experiment ofthis paper as an example, works that needed to be accomplished in days can beshortened to only several minutes using this technology.3. The critical timing problems in project can be solved by clock skewcompensation technology, such as setup timing violation of clock gates, recovery timingviolation of memory, setup timing violation of registers and so on. The experimentsshow that the technology has ovbious optimizing effects on problems above, and hasreceived varying degrees of timing performance improvements.This paper has implemented the clock skew compensation technology based onEDI tool’s useful clock skew optimization and furthurly explored the potential of EDItool’s ability of applying useful clock skew. The technology has provided a practicalsolution and it has important practical value in engineering practices.