Researching And Design Of A 12Bit 4.6MS/s Pipeline ADC

In the digital signal processing chip(DSP),the analog-to-digital converter(ADC)is an important way to connect the analog signal module and the digital signal module.It is the quality of the ADC that directly affects the performance of the DSP.In a hybrid integrated system,the ADC is required to have higher accuracy and lower power consumption.Realizing low power consumption is still the main research direction in ADC design.According to the requirement of a low-power DSP chip,a 12-bit 4.6MS/s pipeline ADC was designed under the condition of 60 MHz main frequency.The ADC includes two 4-bit pipeline sub-stages and a 4-bit Flash ADC,while a 3-bit successive approximation ADC(SAR ADC)is embedded in the second pipeline sub-stage.Specially,we adopt a SHA-less circuit structure in this design,which solves the problem of high power consumption in the sample-and-hold circuit in traditional pipelined ADCs.At the same time,the OPAMP sharing technology is used in the pipeline sub-stage,which reduces the number of operational amplifiers and optimizes the power consumption of the ADC.In order to improve the performance of the ADC,a high-gain and ultra-bandwidth operational amplifier circuit is designed,which uses gain enhancement technology to achieve high gain,and uses deep N-well CMOS tubes to increase the input transconductance,thereby to enhance the gain bandwidth.Next,a high-speed latch comparator circuit is designed.The comparator adopts a three-stage pre-amplification structure to reduce the impact of kickback noise and uses offset cancellation technology to reduce the offset of the comparator.Moreover,aiming at the problem that the change of the process corner will change the output temperature characteristics of the bandgap reference,an adjustable bandgap reference voltage source is designed,and the output stability is improved by adjusting the trimming circuit.Meanwhile,focusing on the problem of poor anti-interference performance in the signal selection circuit,we optimize the control switch by the series switch structure and the method of potential pull-down,which improves the reliability of the switch and weaken the clock feedthrough error.Finally,based on the GSMC 0.188)CMOS process,the overall layout design of the ADC is completed.The simulation verification of ADC is completed by simulation software.Under the3.3V power supply,when the ADC sampling rate is 4.6MS/s,we input a sine signal with a VPP(Voltage Peak-Peak)of 3V and a frequency of 114 k Hz.The simulation result shows that the SNDR is 72.52 d B,the ENOB is 11.8 bits,and the power consumption is 37.4m W.The design meets the performance requirements of ADC.