Study On Energy - Efficient Design Method Of Broadband High Linearity Pipeline Type Analog - To - Digital Converter

High-speed high-resolution analog-to-digital converters (ADCs) are widely used in next-generation wireless communications, radar systems, medical imaging systems, computers and high-performance instruments. These applications require ADCs that achieve both high performance (in terms of high SNR, high SFDR, sub-sampling capability) and low cost (in terms of low power dissipation, small die area), in order to enable power-efficient system design.Among various architectures, pipelined ADCs have been shown to be power-efficient, and can meet the requirements of high speed and high resolution. Design techniques such as opamp sharing, capacitor sharing, and SHA-less, are considered promising techniques for achieving power efficiency. However, the non-reset sharing of the opamp causes a memory effect, degrading the settling accuracy and limiting the linearity of the ADC. In capacitor-sharing, an additional clock phase is necessary to discharge the shared capacitor and reset the opamp, which can limit the conversion rate. While a SHA-less design exhibits advantages with power efficiency, SHA-less ADCs suffer from resistance-capacitance (RC) delay mismatch between the signal path of the sub-ADC and the signal path of the multiplying digital-to-analog converter (MDAC), which limits the maximum input frequency the ADC can handle.In this paper, a new combined front-end based on opamp split-sharing method is proposed to achieve high power efficiency while maintaining high linearity over a large input frequency range. The input signal S/H function is combined into the first MDAC using an opamp split-sharing scheme in order to prevent the aperture error. A method for the design of the split-shared opamp with low on-resistance small-junction-capacitance mode switches is proposed to meet the different gain and bandwidth requirements of both the S/H and the first MDAC. The combined front-end mitigates the memory effect without requiring an additional clock phase for discharging. Furthermore, the opamp split-sharing scheme avoids crosstalk between the signal path of the S/H and the signal path of the MDAC1. The back-end stage consists of two successive 2.5-bit MDACs sharing one four-input operational trans-conductance amplifier (OTA), forming a single 4.5-bit stage for further power reduction.Based on the proposed high-performance and low-power method, a 14-bit 100-Ms/s pipelined ADC is implemented in a 0.18-μm CMOS process, occupying a core area of 6.3 mm2. The test result shows that the DNL and INL of the ADC are within +0.8/-0.7 LSB and +2.1/-2.2 LSB, respectively. The prototype ADC achieves a SFDR of 89.1 dB and a SNDR of 70.2 dB (ENOB=11.4), with a sampling rate of 100 MS/s and an input of 15.5 MHz. For input signals up to 220 MHz, measured SFDR and SNDR are maintained above 82.7 dB and 66.2 dB (ENOB=10.7), respectively. The ADC consumes 92 mW (excluding reference buffers) with a 1.8 V supply, demonstrating a FOM of 0.39 pJ/conv-step.