A 10, 70 Mhz Pipeline Adc Design And Research

Recently, motivated by emerging3rd generation wireless communication and portable consumer electronics, low-power pipelined ADCs employed in these applications, with10to12bits resolution and several tens of MHz clock rate, have become international academic and industrial research focus. Meanwhile, the trend in which analog modules are embedded in SOC requires ADC to be compatible with standard digital CMOS processes which now enter nanometer era and challenge analog design with lower-and-lower supply voltage. However, given a power budget, it is difficult to conciliate speed with accuracy, especially under low supply voltage.This thesis forcuses on the design of low-power low-voltage pipelined ADC by introducing its principle, analyzing some critical idealities, studying low-power design techniques and then exemplifying a10-bit1.2-V70Msample/s pipelined ADC.The proposed ADC ultilizes hybrid time-sharing scheme, i.e. an SHA-less front-end, three2.5-bit stages which shares an opamp, and three following1.5-bit stages which shares another opamp, and a1-bit flash ADC. To cut down the power consumption, the novel time-sharing architecture is innovated to minimize the number of the opamps. Other techniques, including capacitor scaling down, low-power opamp and slew-rate enhancement circuit, are developed to further lower the power dissipation. To maintain high linearity in the case of sub-sampling, the SHA-less front-end adopts RC matched sampling network to minimize the aperture error. Also, opamps are optimized with folded-cascode input stage and switched-capacitor Class-AB output stage, achieving fast and power-efficient operation.The ADC is fabricated in SMIC0.13μm1P8M mixed-signal CMOS process with1.2-V supply voltage, which occupies active area of1.2×0.7mm2. The ADC achieves signal-to-noise-and-distortion ratio (SNDR) of60.4dB and spur-free dynamic range (SFDR) of71.2dB for a33.63-MHz input at sampling rate of70MHz in SS corner while consuming10mW. With a71.64-MHz input, the ADC also achieves71.6-dB SFDR and59.7-dB SNDR, maintaining high performance when sub-sampling...