Research And Design Of High Performance Cmos Pipeline Adc

Pipelined ADC architecture provides an optimal compromise between highresolution and high sample rate in the ADC design, and it is widely used in thecommunication systems. Minimizing power consumption is an important considerationin ADC design with some ways such as removing S/H, opamp sharing and scaling downof capacitors. However, removing S/H leads to aperture time error, opamp sharingcomes along with memory effect and thermal noise needs be considered in scaling downof capacitors.Designing high performance of analog circuits is hard because supply voltage andfeature size is becoming small with the CMOS technology development. However, costadvantage of digital circuit makes the analog design with the help of digital calibrationbe a hot research topic. Digital calibration technology is widely used in the ADC designnow, and relax the analog circuit design and improve the whole ADC systemperformance.This paper present a design of12-bit200-MS/s pipelined ADC with a1.5supplyvoltage which is based on a0.13μm CMOS process. And the4+4+4+3architecture isdesigned. A merged active SHA and MDAC (SMDAC) technique and opamp sharingare used in the ADC. A nested gain boosting technique is first used on the signal path toobtain the required resolution without increasing too much power. A constant-gm biascircuit is designed for corner robustness and a bootstrapped switch is also employed toenhance switch linearity.The gain of OPAMP is98dB, GBW is4.25GHz, phase margin is64degree. theresistance of the bootstrapped switch is smaller than9Ω in the input voltage rangewhich meets the specification; the simulation of the whole ADC shows it achieves72dB SNDR (11.7b ENOB) and87.9dB SFDR while sampling at100MHz, andconsumes500mW. The chip die area is13.7mm2.