The Study And Design Of Low Power Consumption Pipelined ADC Based On Opamp Sharing

ADC is the key device connecting analog world and digital systems. PipelinedADC has become a mainstream architecture for high-performance ADC, because itcan take into account both speed and accuracy. As progressing of CMOStechnology and rapid development of portable electronic devices, low powerconsumption design of pipelined ADC has become a research focus of integratedcircuit design.This thesis uses opamp sharing technology in14bit100MSPS pipelined ADCfor low-power consumption design. This pipelined ADC is designed with0.18μmCMOS technology and1.8power supply voltage. The first-level of this low-powerconsumption pipelined ADC is2.5bit, each level of the second to the eleventh is1.5bit, the last level is Flash ADC of2bit. The SHA of this pipelined ADC ismerged with the first level. The opamp sharing with input multiplexing technologyis used from second level to the eleventh with embedded switch eliminating thenon-ideal effect of opamp sharing. The non-ideal effect of pipelined ADC is alsodecreased by bootstrap switch, capacitor bottom plate sampling switch and virtualtransistor switch. This paper also completed design of SMDAC and other keycircuits.This design is simulating14bit100MSPS pipelined ADC based Chartered0.18μm mixed signal CMOS library. The result is that static power consumption ofthis pipelined ADC is reduced from335mW to175mw with saving47%powerconsumption. When the frequency of input signal is49MHZ, SFDR is93.03dB,SNR is80.40dB, ENOB is13.18bit.