Research And Design Of Low Cost And Low Power Consumption Of Pipeline Analog - To - Digital Converter In Wireless Communication System

Development of wireless communication technology and frequent exchange of mass data between handsets through mobile internet has brought great change to everyday life of people. Power consumption, cost and performance are the three major considerations in the physical layer of wireless communication. As a result, an A/D converter plays an extremely important role in the wireless system for its prominent influence on the power consumption.This work studies the design of A/D converter in the wireless communication system and has built a 50MHz,10-bit accurate pipelined A/D converter. The paper mainly focus on low power and small area design of the A/D converter. We also analyzed the factors that will affect the system performance and accuracy and give the circuit design and simulation result in this paper. We use the following technology to lower the power consumption and cut the circuit area while at the same time achieve satisfying converting performance:saves power and area by op-shared technique.capacitor scaling down technology, and a power source of 3.3V. And saves switches’area by an optimized CMOS switch using depletion mode NMOS devices, reduces opamp’s current and area with thin oxide devices and depletion mode NMOS devices, improves ADC’s accuracy by optimizing timing strategy in MDAC to reduce error produced by op-shared switches.This work Implemented in HHNEC 0.13μm 1P6M CMOS process, this design only occupies a core area of 0.2mm2 and dissipates 45 mW from 3.3V supply. The ADC achieves an SFDR of 78dB, SNDR of 60.7dB (input frequency is 11 MHz) and ENOB of 9.8bit when the sampling frequency is 50MHz.