Design Of A Low Power Consumption Pipelined ADC Used For SoC

In modern digital communication, ADC(analog-to-digital converter) is an important block. With the fast enhancement of system on chip and CMOS fabrication technology, designing a high conversion rate, low power consumption ADC has become one of the current design hotspots.This thesis designed a 1.8V, 10 bit, 100 Msps pipeline ADC with low power consumption based on GSMC 0.18μm technology. The main contents are shown as below:Analyzed and compared current ADC architectures as well as their work characteristics to show the reason why pipeline ADC is suitable for Soc application. Researched and analyzed fundamental principle and design theory of the pipeline ADC. And this thesis analyzed the principle of the mainstream digital correction. Researched current low power consumption technologies used in pipeline ADC, and analyzed their advantages and disadvantages.For the circuit design, taken system power consumption, performance as well as chip area into consideration, this design used 1.5bit cascade structure; and selected charge transfer structure as the S/H circuit in this design by comparing current S/H circuits; meanwhile this thesis designed a high performance gain boosting opamp worked for S/H circuit as well as subsequent sub stages; aiming at the traditional gain boosting switches’ asymmetrical charge injection when it is used as bottom-plate switch, this design proposed a novel gain boosting switch, in the precondition of avoiding breakdown effect and high power consumption, the proposed switch used a pre-charge circuit and a symmetrical structure to reduce switch resistance and notably enhance the sampling accuracy; this design also finished each sub stage, and to decrease total power consumption, dynamic comparator, opamp sharing technique, stage scaling were used; finished band-gap, digital correction, bias circuit as well as clock section; finished the layout of sub-stage included Sub-ADC and MDAC, and digital correction.In normal temperature, entire simulation shows when 5MHz sine signal inputs to the ADC with 100 MHz sampling rate, SNDR is 58.07 dB, SFDR is 65.09 dB, ENOB is 9.51 Bbit. When 21 MHz sine signal inputs to the ADC, SNDR is 54.63 d B, SFDR is 60.44 dB, ENOB is 9.02 Bbit, power consumption is 35.06 mW.