.12-bit The 100msps Pipelined Adc Mdac Module

In this paper, according to the system requirement of 12bit 100MSPS pipeline ADC, the influences of MDAC to the system are considered. The architecture of MDAC based on opamp sharing technique and CFCS (Commutated feedback-capacitor Switching) technique is proposed. The performance of every unit in MDAC is analysed. Further, Capacitor scaling down technique is adopted to reduce system power consumption for better performance.In order to meet the low power consumption requirement, two sequent pipeline stages share an opamp in opamp sharing technique, which reduces the numbers of operational amplifier in pipeline ADC, and saves power consumption and chip area of the whole system. Meantime, in order to get high-resolution, choosing different capacitors as feedback capacaitor in the amplification phase of MDAC according to different input signals in CFCS technique relaxes capacitor matching requirement for manufacturing technology, and improves system linearity.In circuit realization of MDAC, gain-boosted transconductance operational amplifier is used in MDAC. To make sure the stability of the system, Switched-capacitor type and continuous-time type common-mode feedback circuits are designed for main op amp and two additional op amps respectively. The total op amp shared by the first-stage and the second-stage MDAC gets a dc gain of 102dB, unity gain bandwidth of 1.288GHz, and phase margin of 66.6°. Its power consumption is 34.1mW. While, The total op amp shared by the third-stage and the forth-stage MDAC gets a dc gain of 97.8dB, unity gain bandwidth of 691.8MHz, and phase margin of 83°. Its power consumption is 10.3mW.Based on the SMIC 0.18μm/3.3V silicon CMOS process model, every MDAC has been simulated in Cadence simulation environment. The results show that, the first-stage MDAC reaches settling final value of 499.69mV, slew rate of 544V/μ,s and settling time of 4.1ns. Therefore, these MDAC can save power consumption and die-size by adopting opamp sharing technique, and can reduce capacitor mismatching error by adopting CFCS technique.They can fulfill the system requirement of 12-bit 100MSPS pipeline ADC.