Research And Design Of14bit40MSPS Low Power Dissipation Pipeline ADC Adopting Opamp Sharing Technique

Among many electronic applications in modern times, ADC has become the mostimportant building block. With the fast development of communication technology,network technology and electronic technology, the ADC performance we required ishigher and higher. In the field of high speed, high resolution ADC researching, PipelineADC is the most popular architecture for high speed high resolution ADC at present.The biggest advantage of Pipeline ADC is the balance between speed, resolution andpower dissipation. For some portable device, low power dissipation is the key problemfor consideration. So in the thesis, a14bit40MSPS Pipeline ADC with low powerdissipation is discussed and experiment demonstrates its feasibility.First, we introduced the situation in now days and the trend of ADC development inour country and aboard briefly. And then, parameters of ADC performance are discussedin detail. After comparing with different architectures of ADC, the required performancefor high speed, high resolution ADC with low power dissipation is put forward.0.18um CMOS process is applied, designing a14bit40MSPS Pipeline ADC. Thewhole circuit architecture consists of14bit key circuit, reference source circuit, PLLclock frequency doubling circuit, parallel conversion circuit, LVDS circuit, SPIinterface circuit. The circuit is complicated and the parameter of the performance is high.The14bit ADC adopting pipeline architecture, including S/H circuit, OTA, sub-ADCand sub-DAC, redundancy amplifiers, comparator circuit and clock delay digital errorcorrection circuit.The system simulation is the key technology in the circuit design. Especially byusing the device model which is provided by the technology, we can simulate the keycircuit unit, analog digital mixed circuit to ensure consistent. Simulated by the cadencespectre, the Pipeline ADC in the thesis can reach high performance. When the voltage is3.3V, the input range of the analog signal is2Vpp, sampling rate is40MSPS, the SFDRis above75dB and the biggest power dissipation is150mW, complying with the designrequirements.