Design Of Multi-node Upset Hardened Latches For Digital Integrated Circuits

With the development of integrated circuit(IC)manufacturing technology into the era of deep nanotechnology,the integration and performance of circuits have been significantly improved.However,as the critical charge of the circuit node decreases with the increase of the technical scale,and even for ground safety-critical applications,the reliability problems caused by radiation become more and more serious.That is,even low-probability particles in terrestrial environments can cause soft errors.Soft errors include single-event single-node upset,single-event transient,multiple-node upset,and so on.Due to the dramatic reduction of the characteristic size of advanced processes and the charge-sharing mechanism in recent years,the impact of single-event impact may also lead to multi-node upset.If these flips occur in sequential circuits,they can lead to data corruption,execution errors,and even system crashes.This prompts us to design highly reliable anti-soft error circuits,especially in harsh radiation environments for aerospace applications.Aiming at the problem that integrated circuits are susceptible to particle bombardment errors under nanotechnology,this article aims to increase the latch's ability to tolerate double-node upset and triple-node upset.Based on the analysis and summary of previous reinforcement solutions,the design and proposal of two reinforcement latches are proposed:(1)Tripe-node upset-tolerant latch based on three-mode redundancy(HRPDNUL);(2)A novel low-cost TNU-tolerant hardened latch(LCOTNUTRL).The HRPDNUL latch consists of three HRPUL units,three inverters,and a clocked inverter.Each HRPUL is composed of four interlocked C elements.The HRPUL unit can provide good single-node upset self-recovery capability and uses the traditional threemode redundancy idea to combine and optimize the form of the latch to make the latch can fully tolerate triple-node upset.The HSPICE simulation results show that the area overhead is increased by 20.65%,but the delay,power consumption and power delay production are reduced by 25.97%,42.41%,67.57%,respectively.This article also proposes a new type of latch LOCTNUTRL that is completely tolerant to triple-node upset.The proposed single-node upset self-recovery cell performs dual-mode redundancy and uses four inverters at the output.The use of current competition to prevent the propagation of soft errors avoids the high-impedance state due to the use of the C element,and improves the stability of the circuit.The HSPICE simulation results show that compared with the recently proposed reinforced latches,the delay,power consumption,area cost,and power delay production of the reinforced LOCTNUTRL latch presented in this paper are reduced by 57.74%,7.7%,11.74%,and 63.59%,respectively.The process,voltage,and temperature disturbance analyses show that the proposed latch is insensitive to changes so that the latch can be more suitable for aerospace and other critical applications with high reliability.Figure[38]Table[8]Reference[73]...