Research On Single Event Upset Effect Simulationand Verification Technologies

Aerospace craft can be disturbed by radiation in the astrospace. The chip which isthe core part of aerospace craft electronic equipment is more and more susceptible tosingle-event upset (SEU) with the feature size shrinks. There are by far two primaryapproaches for the evaluation of SEU: experiment and simulation. The traditionalradiation experiment costs a lot and lasts for a long time. However, the CAD based SEUsimulation is cheap and can help to evaluate the soft error of the design at thepreliminary stage. Therefore, it is necessary to carry on an in-depth investigation intoSEU simulation approach. Moreover, there is pulse width broadening efect whensingle-event transient (SET) propagate in combinational circuit. In order to get the softerror rate (SER) of a circuit accurately, the effect must be considered in the algorithm ofSER computation. The main works of this thesis are:1. We propose an approach to calculate the propagated SET pulse width byanalyzing the propagation induced pulse broadening (PIPB) effect in combinationalcircuit. The results of calculation are in good agreement with the results of simulation.Compared with Hspice simulation, the max analysis error over Hspice is within4%. So,this will consummate the electrical masking effect algorithm and provide a quantitativeapproach to study the generation of SEU.2. We make use of the basic combinational logic gates and flip-flop to model SEU.Because the SEU model is based on gate level, the speed of simulation using this SEUmodel is fast. In the meantime, the additional control logic in the SEU model can avoidthe error flip of the non-injected flip-flops, so this will improve the accuracy of SEUsimulation by using the proposed SEU model.3. We design the corresponding simulation systems according to the function ofSEU model and the characteristics of software/hardware simulation. Also, they canprovide the statistical output faults which are induced by each flip-flop of a circuit byadding a special module to the simulation system, and the results will guide the designerto harden the sensitive flip-flop in the circuit.To verify the software/hardware simulation system by using ISCAS’95benchmark circuits, the results of these two kinds of simulation systems are the same, and it can beconfirmed that the proposed simulation systems can be used for SEU simulation and theSEU model is accurate. Compared the simulation time of these two systems, the speedof hardware emulation system is at least two magnitudes faster than software simulationsystem. By considering the realizability and simulation time of these two systems, it canbe concluded that for small scale circuits, the SEU simulation can be executed insoftware simulation system; for large scale circuits, the SEU simulation can beperformed in hardware (FPGA) simulation system. Therefore, the need to simulatedifferent scale circuits can be satisfied by the logic gate based circuit level simulationapproach.