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Research On Radiation Hardened And Low Power SRAM Of Nanoscale Integrated Circuits

Posted on:2020-06-25Degree:MasterType:Thesis
Country:ChinaCandidate:M WuFull Text:PDF
GTID:2428330578459464Subject:Integrated circuit engineering
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With the increasing density of SoCs,modern applications need more and more memory modules,which occupy a considerable area of the chip.With the reduction of process,the damage to integrated circuits caused by radiation-induced single event effect increases continuously.When particle passing through the sequential part of semiconductor devices,effects such as funnelling and parasitic bipolar transistor multiply the total charge,such that there is sufficient energy to toggle data stored on a static random access memory(SRAM).This phenomenon is known as a single event upset.Unfortunately,the necessary charge to cause an upset,known as critical charge decreases with process and voltage scaling.Advanced semiconductor technology is more sensitive to soft errors caused by radiation.Furthermore,now that SRAM occupy up to 90% of the die area in modern processors and system-on-a-chip solutions.Therefore,soft error mitigation for SRAM cell has become essential when designing robust systems.In order to enhance the tolerance of the circuit for single event effect,technology of CMOS integrated circuits at nanometer is studied in this paper and a hardened SRAM cell with low power consumption and high reliability is proposed.The main work is as follows:A 12T-SER SRAM cell with soft-error resilience is presented in this paper.It is an access transistor-less architecture and contains the stable structure,which shows high soft error robustness and low power consumption.The proposed design can offer complete Single Node Upset's tolerance of 100% and partial Double Node Upset's tolerance of 64.29% in 65 nm CMOS process.It shows 30.96% lower soft error rate caused by DNU than the classical hardened cell called DICE.In addition,the 12T-SER cell has excellent performance of operating current and power performance,it exhibits a decrease of read current by 77.91%,a decrease of dynamic power by 60.21%,a decrease of static current by 44.60% and a decrease of subthreshold leakage by 27.49% than other previous radiation hardened SRAM cell(such as DICE,Quatro),which is well suited for lowpower applications.When facing the environment variation of noise,voltage and process,the proposed cell also presents less sensitivity.
Keywords/Search Tags:single event effect, single node upset, double node upset, radiation hardened by design, static random access memory
PDF Full Text Request
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