Modeling And Hardening Of Single Event Effect In Integrate Circuit

In radiation environment when high energy ion strikes at semiconductor material charge will deposit along its track. Sensitive nodes collect the charge and induce single event effect. SEE will induce data error and even semiconductor device damage, which will affect the following computing and cause the collapse of the whole system. Statistic of failure shows that SEE is the one of the main reliability challenges in spacecraft electric system.With the advancing of integrate circuit technology, SEU error rate is ever increasing, SET and MBU become important failure modes. The accuracy and speed of traditional modeling technique and the performance and cost of traditional hardening technique show more and more insufficiency. In this dissertation, we aim at the feature of SEE under present semiconductor technology, and study the modeling and hardening of SEE thoroughly. The main works and contributions of the dissertation are as follows1) We propose a novel SEU hardened storage cell. Base on the analysis of chare collection sensitive area and appropriate circuit design, a novel SEU hardening storage cell is presented, which can recovery automatically from single node upset. The storage cell can be fabricated in commercial CMOS process. Therefore it achieves low cost, low power, high speed and high integrity.2) We study the charge sharing collection and its effect to storage cells. By three-dimensional device simulation method, we study the temperature dependency of charge sharing. The simulation results show that the charge sharing collection rise significantly with temperature rising. MBU in SRAM cells and MNU in hardened storage cells induced by charge sharing is analysed in detail. Furthermore, three methods to restrain charge sharing is presented: Enlarging the distance between sensitive nodes, insert guard ring and back-to-back layout style.3) We propose a circuit level coupled SET pulse injection method. Traditional SET independent current source will introduce great error in ultra deep submicro technology. We explored the factors which affect the SET pulse shape and model the SET pulse as a two-dimension lookup table. This method is implemented in open sourced SPICE tool. This method is a well tradeoff between speed and accuracy comparing with independent models and circuit/device mix-mode simulation.4) We propose the SET reconvegence analyse framework in combinational logic, SERAR. In SERAR, reconvergence is classified into 4 mode, ROR, RSUB, RAND and RXOR. For each mode, the sensitized condition based on Boolean difference is presented. Experiments on ISCAS'85 benchmark circuit show reconvergence has significant effect on SER and node sensitivity estimation.5) We design a radiation hardened SRAM based on SOI technology. The design and implement of a 256 32 SRAM with full custom method based on 0.5 m PD SOI technology is described. We complete the whole flow including circuit design, layout design, timing modeling. For radiation hardening, besides the intrinsic ability of SOI, we employ the body tie to improve SEE sensitivity, and edgeless gate to improve TID sensitivity.Finally we forecast the research area of SEE in the future.