Research On Radiation Hardened By Design Latch Of Nanoscale CMOS Integrated Circuits

With the advances in CMOS technology, feature sizes, supply voltages and node capacitances have decreased, leading to the reduction in the charge required to flip the logic value of the nodes. This means that integrated circuits are more vulnerable to single event upsets induced by radiation energetic particle, such as an a-particle or cosmic ray neutron. The scaling of transistor feature sizes decreases the spacing between transistors. Thus, the charge produced by an energetic particle strike may be collected by multiple nodes due to the charge sharing effect, and their corresponding logic values may be flipped, referred to as single event multiple node upsets. As feature sizes entered the era of nanotechnology, single event multiple node upsets has become one of the main failure reason of circuits. The previous single event upsets hardened approaches have been failed in multiple node upsets. Hence, here is an urgent need to develop radiation hardened sequential elements with consideration of double node upsets. In order to improve the multiple node upsets hardened capacity of circuits, this dissertation deeply investigated the single event upsets hardened technology of nanoscale CMOS integrated circuits and proposed a high-efficient robust multiple node upsets hardened design. The main work and innovations of this dissertation are as follows.First, the reliability problems induced by various radiation effects were introduced.With the scaling of technology, the single event upset is becoming more sensitive and the charge sharing is becoming the main failure reason induced by single event effects.Then, the theoretical basis of the main failure mode single event effects were introduced in detailed. The radiation environments, the classification of single event effects and the mechanism of single event upset and charge sharing were investigated thoroughly.This dissertation summarized previous radiation hardened methods for mitigating the soft error caused by single event effects. The circuit-level hardened approaches of single event upsets, single event transients and multiple node upsets were studied thoroughly,and the strengths and weaknesses of previous methods were also analyzed in detailed.Based on research actuality of multiple node upsets hardened technology and the existing problems in previous approaches, a novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets.The proposed latch employs multiple redundant C-elements to form a dual interlocked structure in which the redundant C-elements can bring the affected nodes back to the correct states regardless of the energy of the striking particle. Detailed HSPICE results confirm that the proposed latch features complete resilience to double node upsets and achieves an improved trade-off in terms of robustness, area, delay and power in comparison with previous latches. Extensive Monte Carlo simulations validate the proposed latch features as less sensitive to process, supply voltage and temperature variations.