The Research On Radiation Hardened Technology Of Nanoscale CMOS Integrated Circuits

With the development of the integrated circuit technology in the nanoscale era,the power supply voltage and size of the device are decreasing,and the capacitance of the circuit nodes is decreasing.So the charge of the node drops sharply,so the CMOS circuit is more easily affected by the soft error caused by the radiation effect.When the high-energy particle bombards the sensitive node of the circuit,the charge is collected by the sensitive node.If the node's logic state changes,it is called the single event upset.The technology of IC has been shrinking,transistor size has been decreasing,and the integration of chips has increased rapidly,resulting in the reduction of the distance between transistors.The charge generated by the high-energy particle bombardment circuit may be collected by two nodes,resulting in the simultaneous change of the logic states of the two nodes,which is called single event double node upset.Related research shows that when the characteristic size of IC reaches 90 nm,double node upset caused by charge sharing has become a serious problem.Therefore,designing an integrated circuit against single event double node upset is an urgent problem to be solved.As the size of nanoscale technology continues to shrink,the effect of soft error caused by charge sharing is more and more serious.In order to reduce the soft error of integrated circuits under nanotechnology,in order to reduce the soft errors caused by single node upset and double node upset,2 hardened schemes are proposed on the basis of analysis and summary of previous hardened schemes:(1)TMR-2D1 R,which can partially tolerate double node upset;(2)TMR-1D2 R can be completely tolerant double node upset.The TMR-2D1 R latch consists of 1 RHM cell,2 D-latch cells and 1 majority voter.The latch with tolerant technology the triple modular redundancy,it can tolerate single node upset,and tolerate double node upset partially.Using the good single node upset self recovery capability of the RHM cell,the TMR-2D1 R latch can partially tolerate double node upset.The logic value of the output is still correct when each node in D-latch and RHM is turned over.Compared with the traditional single node upset latch,TMR-2D1 R can not only tolerate single node upset completely,but also can tolerate double node upset partially and improve the fault tolerance performance.The TMR-1D2 R latch consists of 2 RHM cells,1 D-latch cell and 1 majority voter.The latch is also using the fault tolerant technique the triple modular redundancy,it can not only tolerate completely single node upset,and fully capable of tolerating doublenode upset.The traditional triple modular redundancy latch can tolerate single node upset,but cannot tolerate double node upset,using the single node upset RHM cell good self recovery ability,will be the traditional triple modular redundancy traditional latch optimization into mixed form,so that it can tolerate double node upset,effectively improve the fault-tolerant performance of the latch.The result of comparison with the hardened latch with related tolerance double node upset shows that the TMR-1D2 R latch has achieved good tradeoff in delay,power consumption,area and hardened performance.