Resistance To Single Event Upset Of Sram-based Fpga Test System Research And Design,

SRAM-based FPGA devices are becoming of interests for applications under radiation, because they combine low cost with high integration levels and in-the-field programming and updating capability after launch. However, compared with other devices, such as ASICs, untifuse-based FPGAs, SRAM-based FPGAs are more vulnerable to single-event effects, especially single-event upsets (SEU). A huge gap lies between China and aboard in the field of SEU hardening and testing for SRAM-based FPGAs because of the barriers on related technologies. Dependability improving and verification approaches for SRAM-based FPGAs are of increasing interest domestically, and have been listed as one of the national key projects.In this study, a new testing system is proposed for SEU hardening and verification of SRAM-based FPGA, based on the analysis of the mechanism of SEU and the fundamentals of hardening and testing technologies as well. This system, more suitable for domestic experimental conditions, is able to hold both radiation experimental tests and fault-injection emulational tests, and can effectively decrease the complexity and cost of the experimental ones. The sample devices of XCV300 are tested both experimentally and emulationally on this system, and results of the cross section of CLB configuration bits and the hardening effects of triple modular redundancy approach combined with run-time reconfiguration are provided.The results of the tests verified the efficiency and reliability of the proposed system in both emulational and experimental tests. Compared with the existing testing systems, this system needs less supportive equipments, is easier for changing the circuit under test, is smaller in board size, and is more suitable for long-distance controlling. Therefore, it is more convenient and lower in cost for domestic radiation experimental test.