Research On Radiation Hardened By Multiple Node Upstes Design Latch Of Nanoscale CMOS Integrated Circuits

With the semiconductor process size entering the nanometer scale,the distance between the devices decreases,the clock frequency increases and the capacitance of the circuit node decreases,which make the charge sharing effect between the circuit nodes becomes more and more serious.When the integrated circuit device is in a sensitive environment such as radiation,it is easy to be subjected to particle strike to produce single event effect,so that the logic value of the circuit is flipped and the reliability of the circuit is affected.Because of the influence of the charge sharing effect,particle strike easily makes multiple node upsets at the same time,the original hardened scheme of single node upset can't meet the needs of special environment reliability of integrated circuits.In order to improve the reliability of the circuit,it is necessary to study the problem of multi-node upset caused by single event effect.This dissertation analyzes the basic knowledge of single event effect and the harden technique to solve the single event effect,on this basis,put forward two kinds of hardened design for multi node upsets.This dissertation introduces the basic knowledge of single event effect,including related concepts and mechanism research.The generation mechanism of charge sharing effect is analyzed,and some modeling and simulation methods for single event effect are introduced in detail.In order to solve the problem of the circuit reliability caused by single event effect,the circuit should be designed to resist radiation reinforcement.In this dissertation,several hardened circuits design of SRAM circuit,latch and combinational logic circuit are described.Due to the lack of previous hardened design,such as excessive costness and high impedance state problem,can't tolerate double node upsets,etc,this dissertation proposes two kinds of radiation hardened latch: MNUTL latch and HLDRL latch.MNUTL latch is based on the dual mode redundancy mechanisms,its two basic hardened design cells evolution from DICE,the cell can tolerate almost all of the double node upsets.Due to the use of C-element,the soft error is blocked,and can guarantee that the latch can tolerate single node upset and double node upsets.The latch has high robustness and low power consumption.The HLDRL latch is composed of 18 heterogeneous input inverters,which can realize the complete self-recovery of single node upset and double node upsets when affected by single event effect.Compared with single node upset hardened latch,the latch has better robustness,and for double node upsets hardened latch,the latch with relatively small delay and power consumption and there exists no problem of high impedance state,can be used in the clock control circuit.The detailed HSPICE simulation experiment verifies the fault tolerance of the latch,including the problem of insensitive to high impedance state.The HLDRL latch also has lower delay and power cost by comparing other hardened latches.