Digital-Circuit Soft-Error-Rate Estimation And Fault-tolerant Latch Design

With the rapid development of semiconductor technologies,digital circuits become more and more sensitive to soft errors.In recent years,China's rapid rise in the fields such as communication and aerospace has put forward more requirements of high reliability and low cost for digital circuits.In combinational circuits,Single Event Transient(SET)is a main factor inducing soft error rates.In storage circuits,Single Event Upset(SEU)and Double-Node Upset(DNU)are important sources of threats to the reliability of digital circuits.Therefore,it is of great significance and application value to evaluate soft error rates of digital circuits as well as to design SEU and DNU tolerant latches.In order to evaluate and reduce the impact of soft errors on the reliability of combinational circuits and storage circuits,a soft error rate evaluation scheme is firstly designed which considers the influence of many factors,and its speed and accuracy are improved effectively.Secondly,a latch structure which can effectively tolerate double node upsets is designed.The main work of the thesis is briefed as follows:(1)A soft error rate evaluation scheme considering the influence of multiple factors is proposed.Based on the methods of vector propagation and fault probability,the algorithm can automatically evaluate soft error rates of circuits.SET pulses of different effective widths are used to propagate through simulated circuits,and logical masking effect,electrical masking effect,timing masking effect and pulse broadening effect(PIPB)are considered jointly.Meanwhile,when calculating the logical masking effect,the influence of re-convergence effect on the evaluation result of soft error rates is considered,thus improving the accuracy of soft error rate evaluation results.Experimental results show that the proposed method is approximately 54 times faster than the traditional vector method.Moreover,by simulation for small-scale circuit and comparison with Monte-Carlo simulation results,the evaluation accuracy is ensured,and the evaluation difference between them is only 2.96%.(2)A double node upset tolerant latch design is proposed.The design adopts the principle of spatial redundancy for radiation hardening,mainly using 8 C-elements with mutual feedback loops,which can provide effective double node upset tolerance.When a pair of nodes is affected,the logical value of the output of C-elements connected to the node pairs cannot be affected.In addition,the proposed latch adopts clock gating technique,which effectively reduces the power consumption of the latch.The experimental results show can the effective double node upset tolerance.In terms of overhead,the proposed latch can respectively save 51.4% silicon area,52.6% power consumption and 16.3% delay overhead,compared with state-of-the-art latches that tolerance double node upsets.