Research On Single Event Upset And Its Induced Soft Error Of Nano SRAMs

In recent years,the rapid development of aerospace science and technology brings out an urgent request on high reliability microprocessor worked in radiation environment.As the core storage unit of microprocessor,SRAM occupies large area and suffers vulnerability from single event upset(SEU).The soft error in SRAM is mainly brought by SEU,and it makes the microprocessor malfunction.Thus,the research on SEU and its induced soft error in SRAM is very important.With technology scaling down,the charge sharing between the neighboring devices becomes more and more seriously.The serious charge sharing changes the SEU sensitivity of SRAM cells,and makes some exited hardened designs become invalid.In addition,a novel single event effect named SEUR,which can reduce SEU sensitivity,appears in nano SRAM cells.As one of the most effectively method to solve the bottle faced by the traditional SRAM,3D SRAM stacks multi SRAM dies and connects them together with TSV.However,3D SRAM worked in radiation environments also suffers soft errors brought by single event effects.The generation and propagation of SEU in 3D SRAM is more complex than that in the traditional SRAM,which brings difficulty to 3D SRAM soft erorr analysis.Moreover,the incident particles may collide with TSV in 3D structure,which could effect the soft error of 3D SRAM.In this dissertation,we aim at the researches of SEU and soft errors of SRAM cells and 3D SRAM.The main works and contributions of this dissertation are as follows:(1)We study the effect of charge sharing on SEU sensitivity of nano SRAM cells by using full 3D TCAD device simulations.According to the commercial 40 nm SRAM cell layout,all the devices in a SRAM cell are constructed in 3D TCAD models.Based on a great deal of simulations with/without electrical connections and with different LETs,it is found that the charge sharing decreases 37.5% and 65.1% SEU sensitive area for PMOS and NMOS,respectively.The analyses of the charge sharing indicate that SEUR plays an important role on reducing SEU sensitive area of PMOS,and On-PMOS can help collect deposited charge and provide compensation current to reduce SEU sensitivity of Off-NMOS.Moreover,it also finds that NMOS is more sensitive than PMOS in SRAM cells.(2)Using 3D mixed-mode TCAD simulation,we study SEUR between two PMOSs and between Off-PMOS and On-NMOS in a SRAM cell,and the methods to enhance them.According to the simulation results,we find that SEUR between two PMOSs not only depends on the charge sharing but also needs that the charge collection of the passive device must be stronger than that of the active device.Two novel layouts named DSD and DPI are proposed to increase the rate of SEUR.Compared the traditional layout,DSD and DPI reduces 4.26% and 31.56% SEU sensitive area,respectively,under normal incident.For tilted incidence,only DPI layout can sharply increase SEUR rate.Then we study a novel SEUR due to the charge collection of Off-PMOS and the delayed charge collection of On-NMOS.The largest width of SET induced by this SEUR is not related to LET but nearly equals to the sum of inverter delay and SEU generation time.Moreover,the influence of NMOS to this SEUR is more largely than that of PMOS.(3)Aim to get the soft error characteristics of 3D SRAM,we first quantify the effect of 3D SRAM stacked structure on soft error characteristics.The SRIM simulation results show that 3D stacked structure model with six stacked dies would be penetrated through when the energy of the incident heavy ion is more than 22MeV/u.Thus,each die in 3D SRAM may suffer soft error from the heavy ion striking.Then we compare the deposited charge of each die got in the complicated Geant4 simulations.It finds that the difference between the soft error characteristics of upper and lower dies is large in the low energy heavy ions striking,but it is small or even disappears in the high energy heavy ions striking,and serious MCU would existed in lower dies.Moreover,TSV can block the incident heavy ions,and reduce upset cross section for the neighboring sensitive cells.(4)We design a novel 3D SRAM soft error analysis platform,and analyze the soft error characteristic of 3D SRAM via using this platform.This analysis platform bases on the industrial golden simulation methods and tools for SET and SEU,and can get the soft error of 3D SRAM quickly and correctly.Using this platform,we analyze the soft error characteristic of 2D SRAM,the word partitioning 3D SRAM and the bit partitioning3 D SRAM.The analyses results indicate that the cross sections of all 3 kinds of SRAM are the same in the static vertical incident test,but very different in the static random incident angle test.Moreover,in all static tests,there are badly MBU exited in the word partitioning 3D SRAM,so the bit partitioning 3D SRAM is more suitable for work in the radiation environment.In the dynamic test,the combinational logic circuits in all 3 kinds of SRAM may trigger a large number of MBU.In addition,due to the little number of cells around TSV,TSV only can reduce 3% cross section for 3D SRAM.