Design Of A Wide Voltage Input And Low Power SAR ADC

Successive approximation analog-to-digital converter(ADC)can achieve medium conversion accuracy and efficiency.CMOS technology has obvious advantages,which can help to reduce power consumption chip area,and achieve the goal of multiple conversion.In this field,the circuit developed based on CMOS process has certain unique advantages.It can effectively reduce the power consumption,reduce the chip area,and achieve higher conversion efficiency and accuracy while maintaining a cost-effective performance Therefore,it shows a broad application prospect in industrial and medical fields.The work of thesis paper designed a 12-bit CMOS pseudo-differential SAR ADC,a power supply voltage rating(VDD): 2.7 V to 5.25 V,input range: 0 V to 5.25 V,of which the internal digital circuit voltage is 1.8 V(internal DC /DC generation),the input range of the external reference voltage is 1.5 V to VDD,the accuracy is 12 bits,and the low power consumption of 1 MSPS is successively approached to the ADC.It possesses ultra-low power consumption,which is 399 ?A(typical value)at 3 V and 1 MSPS,and has a power saving mode of 3 V and 564 n A(typical value)in power saving mode.Operating temperature range:-40 °C to +125 °C.In order to complete the design and implementation of the ADC,this research work is mainly divided into two parts: 1)Due to the environmental requirements of multiple voltage domains,the design needs to meet the wide range of fluctuation of the analog input,in which the functional level requires to meet the maximum voltage input of 5.25 V.Meanwhile,because the comparator module needs to use low-voltage devices to satisfy the requirements of speed and accuracy,sampling and calculation on low-voltage MOS devices under the input voltage of 5.25 V has become one of the key problems in the design.To solve this problem,a variety of ADC cores have been designed.For realizing the AD function,the high-4 bits independent ADCs and the low-8 bits ADC are used together.Since the high-bit ADC is four bits with a the high-bit 0.25 LSB only.In practical work,there is not high area occupy of the high site AD,and there is not long-term power consumption in high-low ADC also.Therefore,the functional requirements are met and the performances are optimized on the premise of relatively increasing a small amount of area and power consumption;2):In this study,the low-level multistage structure comparator is designed in detail.The comparator consists of two-stage preamplifiers and one-stage latches.In this thesis,the power consumption and gain of all stages of amplifier are designed in detail,which is helpful to reduce the adverse effects caused by backhaul noise.In addition,the misalignment calibration technique is applied to the comparator to realize the effective calibration of the converter to meet the design requirements of the thesis.In addition,this thesis also carries out the research work related on physical layout design by the simulation tool.This design of ADC mainly employs TSMC 0.18 ?m 1.8V / 5V CMOS process with a chip area 2 mm × 2 mm.The simulation results show that,at a sampling rate of 1 MSPS,VREF,input signal and SNDR are 2.5 V,10 k HZ and 73.13 d B(ENOB is 11.8 bits),respectively.|DNL| and |INL| are less than 1 LSB and 1 LSB with a power consumption of 1.2 m W,which has reached the design target of this thesis.