Design Of 12-b 0.18μm Successive Approximation Register Analog To Digital Converter

Analog to Digital Converter(ADC) is widely used in image, sensor, instrument, communication, biological medication etc. Meanwhile, the structure of the ADC is depending on the using field. With rapid advancement of the signal processing technology, the ADCs must have high performance in resolution, speed, power consumption, size, SNDR, SFDR etc.Successive Approximation Register ADC is one of the several kinds of ADCs. For the advantage of simple structure, moderate to high resolution, low power consumption, small size, it is widely used in many applications, for instance, portable instrument, pen input quantization, industry control and data/signal collector etc.The designed SAR ADC that could be used in video and digital camera. Designed and fabricated in the GSMC 0.18μm process, the SARADC is designed to be 12 bits and 15 MSps under the power supply of 1.8V.The designed SAR ADC contains 3 main modules:12bit Digital to Analog Converter(DAC) module: Comparing several different types of DAC and considering the power consumpsion and resolution, we designed the structure of Charge Redistribution with split capacitor that capacitance is the multiple unit capacitance. The LSB, MSB are the same-6bit. The alternative character of the paper is that the Charge Redistribution DAC could have the track/hold function. To assure the ADC’s resolution and sampling precision, we calculate the unit capacitance C and the switch resistance Ron accurately. Meanwhile, bottom plate sampling technology and dummy switch are applied in the circuit which can reduce the charge injection, the clock feedthrough effect and improve the ADC’s performance.High resolution voltage comparator module: Based on the pre-amplifier latch theory, we designed three parts of the comparator module, they are preamplifier, latch comparative stage and output stage. To meet the design requirements, we optimize the pre-amplifier, adopt a dynamic latch structure for the latch comparative stage, and choose the SR latch for the output stage. According to this design method, the comparator could achieve higher resolution and speed. All the conclusions are simulated with GSMC 0.18μm process model, after testing, when the clock frequency at 300 MHz, the resolution of the comparator achieved 39μV.Successive Approximation Register and logic control module: Successive Approximation Register consists of D flip-flops with set and reset function, JK flip-flops and three-state gates. Logic control module generates the control signal that controls the other parts of the system, it contains 16 bits counter, NAND gates and delay modules.All parts of the system are designed on the Cadence. Meanwhile, I accomplish a main module’s layout. At last, using the Cadence and Matlab I simulate the whole system, the final performances are: the ADC consumes 1.84 mW power and achieves 11.46 ENOB at 15 MSps when the input sin wave’s frequency is 500 kHz.