14-bit Non-binary Weighted Energy-efficient Ratio Successive Approximation Analog To Digital Converter

Analog-to-digital converters(ADCs),as a bridge between the analog world and the digital world,have long been the focus of research on digital-analog hybrid integrated circuits.Among them,the analog-to-digital converter(SAR ADC)with successive approximation structure has the characteristics of high repetitive utilization of circuit modules,less required analog circuits,low circuit complexity,simple structure,low power consumption and low cost,and is widely used.In the fields of military,aerospace,medical and control,various industries have also put forward higher requirements for the design accuracy and speed of ADC.This paper chooses the design and implementation of key circuits in SAR ADC as the main research content of the subject.Research and design a high precision,high speed non-binary SAR ADC.Based on the in-depth study of the traditional SAR ADC structure,main operating modes and performance parameters,this paper improves and designs the key circuit modules of SAR ADC by multi-voltage threshold.The main contributions and innovations of the research are as follows:The SAR ADC is constructed using multi-threshold voltage mixing.The digital circuit is connected to 1.2V and the analog circuit is connected to 2.5V.(1)Designed analog circuit modules: including high-performance sampling circuits to reduce the effects of clock feedthrough effects and charge injection problems on the circuit.The non-binary theory is studied,and the proportional parameters required for the 14-bit non-binary SAR ADC are derived.The simulation results show that the non-binary SAR ADC can achieve high energy efficiency ratio and significantly reduce the power consumption of the capacitor on the DAC circuit.Improved high-precision comparator structure,simulation results show that the improved comparator accuracy has been significantly improved.(2)The digital circuit module is designed: the SAR control logic circuit and the clock control logic circuit are realized by designing a combination of different functions and different registers,and based on the existing high-low level conversion circuit,the independent research design proposes a simpler structure.Delay the lower-level conversion circuit to increase the running speed of each quantization cycle of the ADC and effectively increase the sampling rate.(3)Implement the complete SAR ADC circuit layout and calibration algorithm,and pass the functional simulation on the Cadence platform,and pass the performance test on the Matlab platform.A 6-bit non-binary SAR ADC with 3MS/s sampling rate is implemented in a 65 nm CMOS process.The SNDR and SFDR are 80.16 dB and 81.23 dB,respectively.Compared with the performance of similar designs recently published,it has certain performance.The advantages.