Circuit Techniques For Low-voltage Low-power Successive Approximation Register Analog-to-Digital Converter

Low-voltage and low-power analog-to-digital converters are essential componentsin wireless sensor nodes. The size and lifetime of a battery-powered sensor node isdetermined to a large extend by the battery. Low-voltage and low-power circuits enablethe deployment of seamless ubiquitous wireless sensor networks in which each sensornode is expected to consume less than 100μW, cost much less than 1$, have a volumeof less than 1mm3 and be capable of ambient energy scavenging. To achieve this goaloptimization of every component in the sensor node is necessary.CMOS technology down-scaling results in lower voltage swings and transistorintrinsic gain. This trend increases the challenges in designing analog and mixed-signalcircuits. The number of usable analog circuits in nanometer CMOS technologies istherefore restricted forcing the development of alternatives that are amenable to CMOSscaling. This dissertation investigates and applies digital-intensive circuit techniquesto implement low-voltage and low-power successive approximation register analog-to-digital converters for wireless sensor networks and the main contributions are asfollows:An analog-to-digital converter that incorporates a voltage-based comparator isproposed. The rail-to-rail comparator uses parallel combination of complementarysense-amplifiers allowing the inputs to swing close to both supply rails to maximize thedynamic range. A new positive feedback technique is developed that gives a fast andpower e?cient regenerative latch for the comparator.The converter achieves 250KS/swhile dissipating 1.35μW at a supply voltage of 0.8V. The FoM is 34fJ/conversion-step.The second analog-to-digital converter employs a time-based comparator. Theuse of self-timing, voltage presetting and clocked inverters in the voltage-to-time con-verter significantly increase the speed and power e?ciency of the comparator. Thecomparator also includes a new fully di?erential and symmetrical time-to-digital con-verter. The measurement results of the fabricated chip show that, at a sampling rate of 100KS/s and supply voltage of 0.8V, the power dissipation of the analog-to-digitalconverter is 1.92μW and the ENOB is 8.6 bits giving a FoM of 48fJ/conversion-step.The third analog-to-digital converter is a fully di?erential topology that uses anew fully di?erential time-based comparator, a new energy e?cient low complexitycapacitor array switching technique and a ?exible voltage level shifter. The evaluationresults of the converter show that at a supply voltage of 0.6V and sampling rate of100KS/s, the power dissipation is 1.85μW and the ENOB is 9.6 bits giving a FoM of21.1fJ/conversion-step.