Research On Low Power Sequential Approximation CMOS Analog - To - Digital Converter

Analog-to-Digital Converter(ADC), being an essential functional block in the signal processing chain, is widely used in various on-chip systems. In addition, in the application situations such as wireless sensor network, life monitors and portable entertainment, battery life or power durable time has been an urgent issue to tackle. As the feature size continues to decrease, the design of analog circuits is becoming increasingly difficult. Compared with the over-sampling(Delta-Sigma) ADC and pipeline ADC, research on the successive approximation register(SAR) ADC has become a hotspot home and abroad, on account of its simple structure, low power and ease of integration.The breakthrough in the theories of this paper lies in:(1) an energy-efficient switching scheme, named the asymmetrical charge-compensation switching scheme, is proposed. The switching power, the reset power and the linearity of the proposed switching scheme are also discussed in the paper. Compared to the monotonic switching scheme, the asymmetrical charge-compensation switching scheme succeeds in saving 93.8 percentages of the switching power. When the reset power is taken into consideration, a reduction of 81.6% is reached. Besides, the variance of the maximum DNL error corresponding to the proposed switching scheme is optimized to half of that corresponding to the monotonic switching scheme, on condition of the equal matching property of the capacitors.A 10 bit 20-k S/s low-power SAR ADC is fabricated in SMIC 0.18-μm CMOS, at a 0.6-V supply. The SAR ADC adopts the asymmetrical charge-compensation switching scheme to save the power consumed by the capacitive DAC. In addition, the sizes of the transistors in the comparator are adjusted according to the obtained results. When the common-mode input voltage of the comparator changes from 300 m V to 450 m V, the 3×σ offset voltage of the comparator maintains 6m V approximately. The measured results show that, on condition of the Nyquist input, the ENOB of the SAR ADC achieves 9.4bits, consuming only 38 n W.(2) when the dynamic latch-comparator works in the weak-inversion region, the relationship between the input-referred offset voltage and the common-mode input voltageis deduced in theory, and the correctness of the results has been verified by Monte-Carlo simulation. With the aid of the analysis results, the transistor sizes of the comparator are optimized, at the 0.6-V supply. When the common-mode input of the comparator changes from 300 m V to 450 m V, the variation range of the 3σ input-referred offset voltage is only 0.15 m V, 1/8 LSB.(3) the limitations of the operation speed of the SAR ADC is analyzed, and a novel DAC structure that can improve the working speed of the SAR ADC effectively is proposed. A 10 bit 300-MS/s low-power SAR ADC is fabricated in SMIC 65-μm CMOS, at a 1.2-V supply. Because of the trade-off between the power, chip area and the desired working speed, two sub-DACs is presented in the proposed SAR ADC, with one being 5-bit resolution and the other 10-bit resolution. Compared to the conventional structure, only 32 unit capacitors and 74 gate-circuit cells are added. Post-layout simulation indicates that the SAR ADC realizes an ENOB of 9.67 bits and consumes only 1.27 m W, on premise of the Nyquist input.