Research On Key Technologies Of 12-bit 500MS/s SAR-Assisted Pipelined ADC

Due to the broad applications of RF direct-sampling technology,medium-high-resolution analog-to-digital converters(ADCs)running in gigahertz have attracted great attention in wireless and wireline applications.Pipeline ADCs are considered as the conventional candidates under these indicators.However,with the rapid development of integrated circuit technology,the design of pipeline ADCs in nanoscale technology has become increasingly difficult.Pipelined-SAR ADCs are widely used as a substitute.It breaks the limitation of the successive approximation(SAR)ADC in the high-speed and high-resolution.????-??????ADCs are also maintaining the attractive energy efficiency and design difficulty that belong to SAR ADCs.Improving the sampling rate of single channel ADC not only helps reduce the number of channels in a massive time-interleaved(TI)ADC,but also contributes to lower the limitation of overall jitter and input capacitance,imposing a further push on the ADC performance boundary.The residual amplifier(RA)is the core module of pipelined-SAR ADCs,which directly determining the performance of the ADC.Therefore,it is necessary to conduct in-depth research on it.In this thesis,the principle of the pipelined-SAR ADC is introduced firstly with a focus on the study of the residue amplifiers.To meet the design requirements of ADC,a Gm-R-based amplifier is selected as the residual amplifier to replace integrator-type amplifier.Comparing with the traditional open-loop amplifier,the Gm-R amplifier eliminates the sensitivity of the gain variation.Then the non-ideal factors that affect the performance of the open-loop amplifier are analyzed by MATLAB.Based on the amplifier aforementioned,this thesis brings forward a three-stage pipelined-SAR ADC,and the non-ideal effect of the ADC is analyzed and optimized at the algorithm level.Finally,a 12-bit 500MS/s pipelined-SAR ADC with an open-loop Gm-R-Based amplifier is designed in TSMC 28 nm CMOS.The ADC uses a three-stage(4b-4b-6b)architecture with two redundant bits.The “half gain”technique halves the quantization range of the next stage and the gain of the first residue amplifier,thus reducing the design difficulty of the amplifier and increasing the linearity of the circuit.In addition to the research on the gate voltage bootstrap sampling switch,dynamic comparator,residue amplifier,SAR logic control circuit and digital decoding circuit,different CDAC sampling schemes are used to meet the requirements of different substages.Threshold drift technique are used to replace the traditional shift registers and flip-flops to improve the speed of digital circuits and reduce the power consumption.According to the circuit simulation,with the Nyquist input frequency,the pipelined-SAR ADC achieves 62.04-d B SNDR,69.75-d B SFDR,and 9.89-bit ENOB from 0.9 V power supply at 500 MS/s,consuming 6.48 m W,and resulting in 12.16 fJ/conv.step FoM.