Standard Digital Cmos Process, The Research And Design Of High-speed Pipelined Adc

The wide spread of video applications such as digital camera,digital TV, monitor and projector has driven the video processing circuits in to fast development.As a bottleneck module,the high-speed,high-resolution analog-to-digital converter(ADC) has become a hot research issue.This dissertation investigates the implementation of low cost,high-speed,high-resolution pipelined ADCs for SoC applications in standard CMOS logic process.In the system level,a noise model of switch-capacitor pipelined ADC is built to get optimized stage resolution and values of sampling/holding capacitors. A settling error model of the stage circuit is built to optimize the current of the Op amp.Finally,a simple design flow of the power-efficient,high-speed pipelined ADC is summarized.In the device level,the implementation of high performance capacitors in standard CMOS logic process is studied.Two types of practical capacitors,the staggered metal finger capacitor with high area efficiency and the common-plate metal finger capacitor with good matching,are proposed.A 10-bit 110 MS/s pipelined ADC for video front-end is designed and silicon certificated.It is processed in a 0.18-μm standard CMOS logic process with supply voltages of 3.3/1.8V.The ADC integrates a gain-variable widebandwidth T/H and an internal reference circuit.Design techniques such as symmetric bootstrapped switch,bulk-switching switch and OTA with both normal transistors and thick-oxide transistors are developed to get the maximum sampling frequency of 110MHz.The experimental results demonstrate that the DNL and INL are less than 1 LSB and 2.7 LSB respectively.The SFDR of 58.5dB and the SNDR of 47.8dB are achieved at the sampling frequency of 100 MHz.The SNDR is 58.7dB at the sampling frequency of 14.7 MHz.The chip dissipates power of 190 mW and occupies an area of 2.7 mm~2.