Research And Design Of Pipelined-SAR ADCs Based On Dynamic Amplifier

With the development of the times and the deeper understanding of the natural world,more and more simulation quantities need to be recognized concretely.Analog-To-Digital Converter(ADC)will be used in all aspects of life.With today's mobile communication technology has arrived at the high speed era,including medical wearing devices with high accuracy and low power consumption,as well as high-speed and high-precision data transmission devices.Therefore,it is very meaningful and valuable to study ADC with high speed,high precision and low power consumption.Pipelined-SAR ADC has become a research hotspot because single-structure ADC can not meet the needs in many cases.It is characterized by high accuracy and fast speed of Pipelined ADC and low power consumption,small area and high-speed digitization of progressive approximation ADC.The dynamic operational amplifier technology has the characteristics of fast response and low power consumption,which further improves its energy efficiency.In this paper,Pipelined-SAR ADC theory,system architecture and key technologies are analyzed,and a 12-bit 625MS/s Pipelined-SAR ADC is designed.This paper mainly studies the design of residual amplifier,which is a difficult point.A new latch type dynamic amplifier is used,and a gain calibration technique is presented based on its characteristics.On the premise of guaranteeing speed and power consumption,the linearity of dynamic amplifier is improved,and the accuracy and dynamic performance of ADC are improved.This design uses a 28 nm CMOS process with power supply voltage of 0.9V,inputting frequency of 300 MS/s,ENOB is 10.65 bit SFDR,SNDR of 76.12 dB and 65.92 dB.Due to the advantages of the correction algorithm,and the power consumption is only 10.17 mW.