Low-power High-speed Pipelined Adc Used In Digital Video Receivers

Nowadays, DVB-X, Set-top box and high definition TV market are progressively calling for analog-to-digital converter. Since high performance and various functions applied in multimedia systems are required, 10-bit resolution, low power and low cost analog front-end solution handling dense multi-channel operates on a single chip, for example, triple channel application like YUV or RGB capture. As a result of integration of analog and digital circuit with high frequency operation on a single die, high frequency noise is the significant source to degrade the performance of analog-to-digital converter. Low power, low cost and noise free is a hot research on the field of analog-to-digital converter.This work is focusing on pipelined ADC applied for the digital video with 0.18 um 1.8-V logic CMOS process. Above all, system architecture is defined by matlab, according to system requirements, limited parameters of ADC's sub circuits are modeled mathematically. Secondly, based on process characteristics and spice tools, this work presents the transistor level of pipelined ADC. Finally, layout and chip testing are described. The main contributions can be concluded as following:1. There are lots of input reference wires connected to sub ADC of every pipeline stage if sub ADC is operated by conventional dynamic comparator so that reference buffer is significantly disturbed by coupling noise between reference wires. Another big problem is that dynamic comparator bumps up frequently under high-speed switching. Conventional solution is to design a RC filter to eliminate kickback noise with large silicon area. A new circuit is proposed in this work. There is not any input reference in dynamic comparator, so the mentioned problems are eliminated.2. In order to deal with high frequencies inputs, the SHA requires sampling switches with very low and constant on-resistance. A proposed gate-bootstrapping circuit is suitable for low power supply that is 1.8-V power supply used in this work. This circuit decreases the output distortion of switched capacitor circuit. Otherwise, this circuit can be used in logic CMOS process to reduce silicon cost.3. An important problem, conventional 1.5-bit per-stage pipelined ADC operated in low power supply although there is 0.5 bit redundant correction (RSD) in the range of ± 1/4Vref, is that overall linearity of the converter is degraded by deceasing power supply. This work proposed an interpolated-redundance correction to enhance overall linearity of pipelined ADC. Based on definition of system level and process characteristics, The solution is to insert an interpolated-redundance correction stage, and then convert an input range larger than ± V_vef that is accumulated from first stage to the i^th stage into norminal range from -V_vef and +V_vef to avoid the overall distortion.4. Being compatible with logic CMOS process, MDAC has not high linear MiM capacitor but stack capacitor. Be careful layout extraction to guarantee the overall linearity of analog-to-digital converter.5. Operational amplifier sharing is based on the fact that in switched-capacitor architecture, the amplifier is used for only one half of a clock cycle, which is during the amplification phase. This way, the same amplifier could be used during different clock phases. This sharing technique can reduce power consumption and silicon area significantly.This dissertation has two silicon experiments. One is fabricated by 0.5um DPTM CMOS process for 10-bit 1MS/s pipelined ADC. The experimental results prove the error analysis and matlab models suitable for pipelined ADC. The other silicon experiment is fabricated by 0.18um 1.8-V single poly six metals logic CMOS process for 10-bit 100MS/s pipelined ADC. For testing environment, this work sets up testing environment of high-speed ADC and PCB design. These two experiments present two sampling rate 10-bit pipelined ADC with different process, featuring 0.8/0.55 LSB INL and 0.71/0.47 LSB DNL, 9.7/9.3 ENOB, 1.7/0.98 mm², 45/63 mW. The second Experiment shows 0.995 pJ. V²/Sa FOM and 1.55e-11 mm²/Sa FOM_A, Such the level of performance reach high level of research on pipelined ADC reported in JSSC and ISSCC et al during the recent years and is sufficient for video analog front-end and other receiver operations.