Research On Key Technologies Of16-bit High-Speed CMOS Pipelined Analog-to-Digital Converter

The analog-to-digital converters (ADC) have been widely used in wirelesscommunication system, radar and other electronic information systems. Along with thearrival of the new generation of wireless mobile communication, the digital IF receiverof the communication system requires a higher performance of ADC. The PipelinedADC, which gives consideration to both speed and precision, is good choice to adapt tothis requirement.Pointing at the high requirement for ADC by wireless communication field interms of switching precision, speed and dynamic performance, this research hasdesigned a16-bit100-MS/s sampling rate CMOS pipelined ADC through the studiesand the optimization of Pipelined ADC system construction and key modules.Based on the analysis and parameter modeling of system noise limitation and mainpower blocks, this research acquired the systematic precision distribution of optimized16-bit pipelined ADC. Meanwhile, in accordance to the requirement of system noise,this research also determines the size of the sampling capacitor for each stage.According to the above system structure, some optimization design methods areproposed as follow:An improved digital redundancy has been proposed, which uses the technologiesof averaging sub-quantization and scaling down the output of stages, in order to bothkeep the function of traditional digital correction algorithm and also to improve thelinearity in conversion. In addition, the new algorithm also introduces negative andpositive redundant bit so as to determine overflow.A new fast-locking, low-jitter and high-precision CMOS pulsewidth control looprealized by delay locked loop is designed. By using the single edge of clock, theproposed circuit achieves the modulation of duty cycle, and also substantially reducesthe complex of the circuit and the clock jitter.Amulti-stage pre-amp comparator with offset-cancellation is proposed, which meetsthe requirement of low input offset voltage and high conversion rate.A sample-and-hold circuit of high speed, high resolution and high spurious freedynamic range is designed by using an improved bootstrap sample switch and again-boosted pseudo differential operational amplifier.An analog calibration is proposed. In this calibration, a post-production capacitormismatch extraction method is designed. Then the non-linearity error caused by capacitor mismatch in multi-bit sub-DAC would be calibrated with a high correctingprecision.Based on above designs, a16-bit100-MS/s pipelined ADC is realized in SMIC0.18μm1P6M CMOS process. The active area of the ADC is16mm2. Simulationresults show that under3.3V supply voltage, the power dissipation is750mW. At100MS/s, the ADC achieves98.25dB of SFDR,87.78dB of SNDR and14.25bits of ENOBfor an input signal of50MHz. The proposed converter is the advanced level in thisdirection.