Digital Calibrated Pipelined ADC Design In Nanometer CMOS

Analog-to-digital converter (ADC) is one of the most critical components in signal processing systems. In recent years, because of the rapid blooming of computer and communication industry, there is a constant increase in demand for the performance requirement of ADCs. Meanwhile, with the technology advance of CMOS process brings both opportunities and challenges to high-performance and low-power ADC design. Pipelined ADC is more attractive for communication applications nowadays, due to the potential of combining high resolution and high sampling rate.This dissertation is focusing on pipelined ADC design with nanometer CMOS technology and reduced power supply. A pipelined ADC, employing digital calibration technique and low-complexity analog circuits, on 65nm CMOS process and with 1.2V supply voltage is designed, fabricated and tested. This work can be summarized as follows:1. Based on the circuit-level modeling of pipelined ADC, the impact of amplifier non-ideality and MDAC capacitor mismatch on ADC linearity is systematically analyzed, which also reveals the limit of conventional pipelined ADC structure in nanometer CMOS technology.2. Digital calibration technique for pipelined ADC is investigated, and two novel algorithms, i.e. virtual-ADC equalization technique and offset split ADC technique, are proposed, which can adaptively compensate for residual amplifier impairments and MDAC capacitor mismatch, and therefore improve the ADC linearity. By moving the design complexity from analog domain to digital domain and benefiting from CMOS technology down-scaling, such digital calibration technique significantly reduces analog circuit complexity, as well as the power consumption.3. Equalization-based digital calibration technique is proposed, in which various non-idealities in multi-stage of pipelined ADC can be calibrated concurrently with only a single test signal. This approach shortens the calibration time, reduces the circuit design complexity and testing cost, as well as improves the ADC linearity. The test result shows the virtual-ADC equalization calibration takes only 2M samples or 0.01s to achieve 12-bit resolution requirement. Furthermore, it provides a new method to achieve high-resolution and low-power in various ADC architectures.4. The design methodology of low-power pipelined ADC is studied. A 12-bit, 150MSPS ADC prototype assisted by the virtual-ADC equalization technique was fabricated on 65nm CMOS with 1.2V supply and 48mW power consumption. And the measured performance, e.g. power consumption, linearity, has satisfied the design specifications, indicating the effectiveness and robustness of the proposed design methodology.In order to verify the proposed design methodology, a 12-bit, 150MSPS, 9-stage, pipelined ADC prototype assisted by the virtual-ADC equalization technique, which is proposed in this thesis, was fabricated on 65nm CMOS. The measured performance shows that by employing digital calibration, the SNDR is improved from 28dB to 67dB, and the SFDR is improved from 33dB to 81dB with a 6MHz input signal. The ADC core consumes 36mW from 1.2V power supply, and the digital calibration is implemented in software and the estimated power of this part is 12mW.