Design Of 12 Bit High Speed High Precision Pipelined ADC

In recent years, the high speed high precision analog-to-digital converters are widely applied in the field, such as high quality video signal disposal, high performance digital communication and medicine imaging. The research on the circuit structure and the process technique is carried out to satisfy the demands, especially, the investigation on the ADC manufactured with standard CMOS process. The design and the fabrication of ADC develop to low power, high speed, and high resolution. Due to its high precision and high sampling rate, research and design on pipelined ADC are widely attention to.The 12 bit high speed high precision pipelined ADC is designed with 0.18μm standard CMOS process in the thesis. The pipelined ADC mainly includes the analog circuit part and the digital circuit part. The analog circuit and the producing clock circuit are mainly designed, and the theoretical analysis of the digital error correction is in detail carried out. The ADC is mainly composed of 11 level pipelines. The similar structures of first 10 levels are 1.5 bit, including dynamic comparator, sub-DAC and residual error amplifier, and the last level is 2 bit ADC. Firstly, based on the deeply research on the principle of circuit, the system design of ADC are carried out. Simulation and analysis on the whole circuit are accomplished. According to non-ideal factor affecting the ADC performance, the circuit structure is given during improving the influences of the non-ideal factors. Then, design and simulation of the dynamic comparator, sub-DAC, the CMOS operational amplifier, the switching circuit, the MDAC circuit and the producing clock circuit are in detail described. And the simulation results are analyzed to assure the performance index of designed circuit. Finally, the problems about layout design in analog part are discussed, and layout design and verification are accomplished.The major performance indexes of whole circuit include 12 bit resolution, 100MSPS highest sampling rate, 1.8V power supply, and 80mW power. The differential inputs are applied, the linearity is good. INL is less than 0.5LSB, and DNL is less than 0.5LSB.