A Study Of High Performance CMOS MDAC

Over the past two decades, silicon integrated circuit(IC) technology has evolved so quickly. Transistors become faster and faster with the shrinking channel length of the transistors. The evolution of IC technology has caused great changes to digital circuits in industry. As IC fabrication technology has advanced, lots of analog signal processing functions have been replaced by digital blocks. In spite of this trend, analog to digital converters(ADC) retain an important role in most modern electronic systems because most signals of interest are analog in nature and must be converted to digital signals for further signal processing in the digital domain.Pipeline ADC has better tradeoff among speed, accuracy and power consumption, therefore it is widely used in high speed and high accuracy field such as wireless communication, HDTV, image processing and digital communication. MDAC is the key circuit module to the pipeline ADC, so its precision and speed restrict the performance of the entire ADC system. This thesis analyses and designs the MDAC of the high speed and high accuracy ADC. By analyzing the system structure of the 14 bit high speed and high accuracy ADC, the system’s architecture is determined. The 14 bit pipelined ADC includes SHA, 3 bit first stage, four 2 bit stages and 3 bit flash. The dissertation focuses on the principle of typical MDAC circuits and analyses errors and non-ideal effects on MDAC and then gives the corresponding solutions which lay foundation for the further MDAC design. Noise has key influence on ADC’s performance. The sampling capacitor of the first MDAC is determined by analyzing the quantization noise and thermal noise. By analysing the static error and dynamic error of a high speed and high accurcy ADC, the operation amplifer of the first MDAC needs extremly high gain and GBW. In order to release the op-amp, the dissertation proposes a scaling down technique. The stage gain of the first MDAC is reduced by half and the feedback factor is increased by half, thus the requirement on gain and GBW of the op-amp is reduced by half. Operation amplifier being the key block of the MDAC, in order to improve the performance of the MDAC, a high gain and high GBW op-amp is designed. The comparing voltage of the comparators and the voltage needed by the MDAC is generated by the reference voltage circuit. So in order to remain more time for the op-amp settling, the reference voltage must be settled more quickly and hence much better. To obtain the settling speed, the reference voltage circuit consumes much power. By elaborately designing each stage, the pipeline ADC only needs one reference voltage and the other reference voltage on the ground, then the power consumption is reduced.The circuit is designed on SMIC 0.18μm 1.8V CMOS process and simulated in Cadence. Cadence simulation results indicate that the DC gain of operational amplifier is 92.02 d B; the closed loop bandwidth is 1.2GHz; the phase margin is 61.5o and the GBW is 3.43 GHz. The input frequency of the input signal being 10.7421875 MHz, the Vpp being-1d BFS(FS=1.5V)and sampling points being 256, the converting result of the first MDAC is SFDR 94.93 d B, SNDR 83.70 d B. and the ENOB13.61 bit.When the input frequency is 170.8984375 MHz, the converting result of the first MDAC is SFDR 81.23 d B, SNDR 71.90 d B and the ENOB 11.65 bit. All the performance parameters are satisfied the 14 bit pipelined ADC. The whole power consumption is 400 m W. The area of the layout is 3.5×3.2mm2.