Low-Power Research On Residue Amplifier Applied To Pipelined-SAR ADC

As the bridge between the analog world and digital world,ananlog-to-digital converter has become one of the mix-signal electrical products in greatest demand,which is widely applied in our life and work,such as telephone,computer,wearable devices and WiFi,etc.With the rapid rise of the Internet of Things?IoT?,intelligentialize and hommization now become the main development direction of electrical devices,which puts forward more harsh demands on the power design at the same condition of resolution and speed.Pipelined ADC can achieve both high resolution and high speed,but it also has a problem of high power consumption.A low power ring amplifier is proposed in this thesis as the residue amplifier of pipelined architecure to overcome the power-ineffiency drawback,and with SAR ADC as the sub-ADC of the pipelined stage,pipeliend-SAR ADC is realized in the latter part of this dissertation to test the working condition of the ring amplifier.The research status of ADC and the performace metrics are introduced in the first two chapters;then a summary of the features and its main application is followed.Based on the demand of ADC,this thesis has made a prediction of ADC development in the second chapter.Since the residue amplifier contributes the most power cost in a pipelined ADC,a new self-biased pseudo-differential ring amplifier is proposed to achieve medium-high speed,medium-high resolution and low power with an innovative and detailed optimization among speed,resolution and power.And the problem of charging sharing has also been solved to eliminate the gain error.Besides,this dissertation makes an analysis of three different types of ring amplifier.Two SAR ADCs are adopted in the pipelined-SAR ADC,which are bottom-plate sampling SAR ADC and V_CM-back SAR ADC.The SAR logic and comparator are redesigned and realized in the circuit.The pseudo-differential ring amplifier has serized two SAR ADC to realize a 12bit,160MS/s pipelined-SAR ADC with TSMC 40nm technology.The gain of the ring amplifier is around 15.92±0.008 under the power of 800?W.The speed is 160MHz,and SFDR>85dB with rail-to-rail output.The resolution of the two SAR ADC is 5bit and 8bit,respectively,and their ENOB are 4.92 and 7.38 at the sampling frequency of 400MS/s and 160MS/s.The ENOB of the pipelined-SAR ADC is 9.1bit,SNDR=56.6dB.The figure of metics?FoM?is 34fJ/conv-step.