Design Of High Speed And Low Power Pipelined-SAR ADC

High-speed and high-precision analog-to-digital converters(ADCs)are widely used in image processing,information storage and wireless communications,However,in the fields of industrial control and communication industries in recent years,its high-speed chips often require very powerful endurance capabilities.Pipelined-successive approximation analog-to-digital converter(pipelined-SAR ADC)can achieve high-speed and high-precision performance while maintaining low power consumption,so it has become a major research hotspot at Domestic and foreign in recent years.The main work of this thesis is to research and design a 12-bit 50MS/s low-power pipelined-SAR ADC based on 180 nm CMOS process.The system can be regarded as a two-stage successive approximation analog-to-digital converter(SAR ADC)cascade.The accuracy of the first stage SAR ADC is 8 bits,and the second stage is 6 bits.It sets two-bit redundancy and inter-stage amplifier gain is 16.The first stage SAR ADC adopts a 2bit/cycle conversion method to increase the conversion speed due to its compact time;the second-level SAR ADC uses a capacitor DAC structure in the form of a split capacitor to reduce the number of capacitors of the second stage SAR ADC;Aiming at the residual amplifier between the two-stage SAR ADC,this article uses a dynamic amplifier to reduce power consumption.In order to achieve the high gain requirement of 16,this article designs a latch type dynamic amplifier and combines it with an auxiliary operational amplifier.,A dynamic amplifier with high gain and high linearity is realized;Aiming at the problem of gain instability of the dynamic amplifier,this thesis designs a front-calibration scheme,which does not add additional input signals and has simple timing.The structure of the two-stage SAR ADC is used to calibrate the gain of the dynamic amplifier.In addition,this thesis also designs some key modules such as dynamic comparators,asynchronous sequential logic,digital code error calibration circuits,etc.Layout of the pipelined-SAR ADC designed.The final chip core area is430um×850um.The post-simulation results show that under 1.8V power supply voltage,when the sampling rate is 50MS/s,the input signal is a sinusoidal signal with 24.8MHz and amplitude of-1d BFs,the ENOB of the designed ADC reaches 11.1562 and the SFDR is 76.252 dB.