Digital Pulse Width Modulator Based On Multi-phase Phase-locked Loop

Along with the requirements for the smart,configurable,product design and iteration cycles of integrated circuits for DC-DC converters,digital switching mode power supplies have received extensive attention.Its loop control is formed in a digital way,with configurable parameters,short design cycle,flexible application environment,and real-time monitoring of working status.Digital Pulse Width Modulation(DPWM)is a key part of the digital DC-DC controller.Its performance determines the DC-DC output voltage range,accuracy and ripple size,so the realization of high-precision DPWM is a design key that deserves attention.This article discusses the characteristics of counters,delay chains,and hybrid DPWM structures,and compares several common DPWM high-precision implementation schemes.In order to achieve high precision while reducing the system clock frequency as much as possible,the phase-shifted by phase-locked loop scheme is finally adopted.Based on the design requirements of the phase-locked loop of the DPWM circuit,this artical analyzes the calculation method of the loop parameters of the charge pump phase-locked loop,and verifies a set of loop parameters through behavior-level modeling.Then this article implements a DPWM circuit based on multi-phase phase-locked loop,,give out the curcuit schemes of phase-locked loop,digital coarse modulator,bandgap and voltage regulator.The phase-locked loop adopts the ring oscillator of the differential structure to realize the clock signal of 16 phases.Oscillator bias is generated by a bias generating circuit with negative feedback,which can reduce the influence of power supply ripple.The clamp buffer of the charge pump uses a rail-to-rail amplifier with a full input range and constant gain to expand the working range of the charge pump without being affected by the amplifier.The overall DPWM circuit adopts a digital-analog hybrid design,which is divided into two stage of modulation: the first coarse modulation based on the counter and the second fine modulation based on the 16-phase clock of phase-locked loop.The first stage generates a coarse pulse width modulation(PWM)signal with a pulse width accuracy of 4ns and superimposes the phase shift signal of the second stage to realize a PWM wave with sub-clock cycle accuracy.The 11-bit DPWM circuit designed in this article is based on the GSMC-0.18 um CMOS process.The circuit design,simulation and layout are completed by using design tools such as cadence and matlab.The phase noise frequency deviation of the voltage controlled oscillator is 104 d Bc-106 d Bc@1MHz.The lock time of the phase-locked loop is 10-13 us,the phase deviation of different output is less than 2ps.the total jitter(P-P)is 113 ps.DPWM simulation results show that its resolution is 250 ps,the switching frequency is2 MHz,and the pulse width deviation is less than 48.2ps when the duty cycle is in the range of 0.0024-99.95%.