Research And Design Of High Performance Charge Pump Phase Locked Loop

With the increasing amount of information,higher requirements are placed on the transmission rate and transmission bandwidth of current communication systems.Therefore,high-speed,wide-band frequency synthesis technology has been widely researched and applied.Common frequency synthesis techniques include direct frequency synthesis,phase-locked loop frequency synthesis,and direct digital synthesis.Compared with other frequency synthesis technologies,the PLL frequency synthesizer has the characteristics of high output frequency,low phase noise,and simple circuit structure.In modern optical communication technology,Ser Des transceiver system is inseparable from high-performance phase-locked loop.Therefore,the research and design of phase-locked loops still have high research value and commercial value.Based on the 40 nm CMOS technology,this paper designs a high-speed,broadband charge pump phaselocked loop for Ser Des transceiver chip.The phase-locked loop adopts an integer frequency divider for frequency control,inputs a reference clock of 180 MHz,and outputs a clock signal of 14.4-20.88 GHz.In the design,the two key modules of traditional switch-type charge pump and voltage-controlled oscillator are optimized to improve the performance of the phase-locked loop.The charge pump circuit adds a replica branch and a high-gain rail-to-rail operational amplifier on the basis of the source switch to achieve accurate matching between the main branch and the replica branch.The static mismatch current within the operating voltage range is less than 0.1%.During the transient process,the transient mismatch is controlled to a small value by adding a Dummy switch.VCO is based on the VCO,which uses binary control switched capacitor array to widen the frequency modulation range of the loop output signal,add bypass filter circuit to optimize the noise performance,introduce tail current source to control the power consumption of the circuit and reduce the impact of process and temperature on the working current.At the center frequency of10 MHz,the phase noise of the VCO is less than-114.66 d Bc / Hz.The frequency divider adopts the combination of high-speed CML frequency divider and low-speed programmable frequency divider.It is used to divide the high-speed clock signal to achieve continuous integer frequency division of 64 to 126.The programmable trigger is calibrated by synchronous trigger Stage delay to reduce the phase noise and clock jitter of the crossover.A three-state PFD structure is used to widen the phase detection range,and the phase detection performance is not limited by the duty cycle of the input signal.The post-simulation results show that the PLL can work normally under all process angles.In the tt process angle,the power consumption of the phase-locked loop is less than 32 m W,and the lock time is less than 400 ns.The phase noise of the PLL loop is less than-109 d Bc / Hz @ 18 GHz @ 1MHz,and the reference spur at the center frequency is less than-56.7d Bc.The overall layout area of the PLL is 480?m × 480?m.