The Design And Implementation Of Self-biased Phase-locked Loop

The phase-locked loop (PLL) is widely used in digital integrated circuits as a clockgenerator, in the wireless communication system as a frequency synthesizer and in thedata clock recovery circuit. High-performance PLL research and its applications is also ahot spot in the field of today’s integrated circuits. The research subject of this paper is theself-biased PLL uses as a clock generator in the image-processing ASIC, and because ofthe high portability of the self-biased PLL future, it could also use in other SoC or ASICchip, therefore it has important research significance.This article describes the building blocks and the linear mathematical model ofsecond-order CPPLL. Then analysis and derive closed loop transfer function of theCPPLL, and two loop parameters: the natural frequency?Nand damping factor?.Discusses the influence of these two parameters on the PLL system, and give theconditions of the circuit parameter that fit the need of the fixed damping factor? and thefixed rate of?N/?REF. Through analysis the principle of self-biased technology and linearmathematical model of the PLL, the two loop parameters?Nand? are constant, and showthat the self-biased phase-locked loop has good portability.In order to improve the level of integration and ease compatible with digitalmanufacturing process, loop filter of the PLL use CMOS device capacitance. The loopfilter resistor instead of using the passive resistance, but to achieve by the symmetricalload unit structure, avoiding the impact of the loop because of the imprecise of passiveresistance. So as to prevent the effect of the dead zone, add certain delay in the resetpath of the PFD module. Bias generator circuit achieves two functions: First, accordingto the working condition of the system to create a dynamic bias point, realize theself-biased function; second by using the superposition principle achieve theproportional-integral loop filter function. The zero offset charge pump constitute withdifferential delay unit; voltage-controlled oscillator adopt four-stage ring oscillatorstructure.The subject decompleted the design and simulation of the self-biased PLL circuit, thedesign of layout, and fabricated in a0.18μm CMOS logic process. The final test results show that the clock generator is able to achieve the four frequency output, to achieve thedesired design specifications, and could be used as image process ASIC and SoC clockgenerator.